公开(公告)号：EP1763238A3

公开(公告)日：2009-07-15

申请号：EP06250838.7

申请日：2006-02-16

Applicant: Fujitsu Microelectronics Limited

Inventor： Iga. Kiichiro

IPC: H04N5/77

CPC classification number: H04N21/242 ,  H04N19/60 ,  H04N21/23406

Abstract: An image processor for lowering data transfer speed. A JPEG compression circuit (34) performs two-dimensional compression process on data (S1) output from a YCbCr conversion circuit (31) to generate compressed image data (S3). A timing signal generator (37) changes the frequency of a transfer clock signal (TCK) in accordance with the compressed image data (S3). An output circuit (36) outputs the compressed image data (ED) in accordance with the transfer clock signal (TCK).