公开(公告)号：EP2110952A1

公开(公告)日：2009-10-21

申请号：EP09164948.3

申请日：2003-10-21

Applicant: Fujitsu Microelectronics Limited

Inventor： Shimizu, Yoshiaki ,  Suzuki, Hisao ,  Ito, Kenji ,  Kijima, Masashi

IPC: H03M1/16 ,  H03M1/36

CPC classification number: H03M1/0675 ,  H03M1/08 ,  H03M1/165 ,  H03M1/168 ,  H03M1/366 ,  H03M1/42 ,  H03M1/765

Abstract: A current-mode multi-residue multi- stage ADC ( fig. 14 and 15 ), each stage being a 2-bit current flash converter. The first stage (32) generates (N20-N23) four copies of the input current and subtract to them four reference currents (I20-I23) corresponding to the four quantization levels of the first stage. The currents which are result of the subtraction are input to comparators (C01-C03) and an encoder (35) for generating the digital output (D3-D2) of the first stage and each to a corresponding one of second stage units (32a-32d) for lower-bit conversion. Each of the second stage unit has the same structure as the first stage.

Abstract translation: 电流模式多残留多级ADC（图14和15），每级是2位电流闪存转换器。 第一级（32）产生输入电流的四个副本（N20-N23），并将与第一级的四个量化级相对应的四个参考电流（I20-I23）相减。 作为减法结果的电流被输入到比较器（C01-C03）和用于产生第一级的数字输出（D3-D2）的编码器（35），并且每个到第二级单元（32a- 32d）用于低位转换。 第二级单元具有与第一级相同的结构。