公开(公告)号：US09823499B2

公开(公告)日：2017-11-21

申请号：US15336489

申请日：2016-10-27

Applicant: Futurewei Technologies, Inc.

Inventor： Qianfan Xu ,  Xiao Shen ,  Hongmin Chen

IPC: G02F1/025 ,  H01L29/66 ,  H01L29/94

CPC classification number: G02F1/025 ,  G02F2202/104 ,  G02F2202/105 ,  H01L29/66181 ,  H01L29/94

Abstract: A metal-oxide-semiconductor (MOS) type semiconductor device, comprising a silicon substrate, a first cathode electrode and a second cathode electrode coupled to the silicon substrate and located on distal ends of the silicon substrate, a poly-silicon (Poly-Si) gate proximally located above the silicon substrate and between the first cathode electrode and the second cathode electrode, wherein the Poly-Si gate comprises a first post extending orthogonally relative to the silicon substrate comprising a first doped silicon slab, a second post extending orthogonally relative to the silicon substrate comprising a second doped silicon slab, wherein the second post is positioned so as to create a width between the first post and the second post, an anode electrode coupled to the first post and the second post and extending laterally from the first post to the second post, and a dielectric layer disposed between the first silicon substrate and the second silicon substrate.

公开(公告)号：US09563014B2

公开(公告)日：2017-02-07

申请号：US14680175

申请日：2015-04-07

Applicant: Futurewei Technologies, Inc.

Inventor： Huapu Pan ,  Hongmin Chen ,  Xueyan Zheng

IPC: G02B6/122 ,  G02B6/30

CPC classification number: G02B6/1228 ,  G02B6/1223 ,  G02B6/305

Abstract: An apparatus comprising a thick waveguide comprising a first adiabatic tapering from a first location to a second location, wherein the first adiabatic tapering is wider at the first location than at the second location, and a thin slab waveguide comprising a second adiabatic tapering from the first location to the second location, wherein the second adiabatic tapering is wider at the second location than at the first location, and a third adiabatic tapering from the second location to a third location, wherein the third adiabatic tapering is wider at the second location than at the third location, wherein at least a portion of the first adiabatic tapering is adjacent to the second adiabatic tapering, and wherein the first adiabatic tapering and the second adiabatic tapering are separated from each other by a constant gap.

Abstract translation: 一种装置，包括厚波导，其包括从第一位置到第二位置的第一绝热锥形，其中所述第一绝热锥形在所述第一位置处比在所述第二位置处更宽，以及薄平板波导，其包括从所述第一位置到所述第一位置的第二绝热锥形 位置到所述第二位置，其中所述第二绝热锥形在所述第二位置处比在所述第一位置处更宽，以及从所述第二位置到第三位置的第三绝热锥形，其中所述第三绝热锥形在所述第二位置处比在 所述第三位置，其中所述第一绝热锥形的至少一部分与所述第二绝热锥形相邻，并且其中所述第一绝热锥形和所述第二绝热锥形彼此间隔一定间隙。

公开(公告)号：US09507180B2

公开(公告)日：2016-11-29

申请号：US14071327

申请日：2013-11-04

Applicant: Futurewei Technologies, Inc.

Inventor： Qianfan Xu ,  Xiao Shen ,  Hongmin Chen

IPC: G02F1/035 ,  G02F1/025 ,  H01L29/66 ,  H01L29/94

CPC classification number: G02F1/025 ,  G02F2202/104 ,  G02F2202/105 ,  H01L29/66181 ,  H01L29/94

Abstract: A metal-oxide-semiconductor (MOS) type semiconductor device, comprising a silicon substrate, a first cathode electrode and a second cathode electrode coupled to the silicon substrate and located on distal ends of the silicon substrate, a poly-silicon (Poly-Si) gate proximally located above the silicon substrate and between the first cathode electrode and the second cathode electrode, wherein the Poly-Si gate comprises a first post extending orthogonally relative to the silicon substrate comprising a first doped silicon slab, a second post extending orthogonally relative to the silicon substrate comprising a second doped silicon slab, wherein the second post is positioned so as to create a width between the first post and the second post, an anode electrode coupled to the first post and the second post and extending laterally from the first post to the second post, and a dielectric layer disposed between the first silicon substrate and the second silicon substrate.

Abstract translation: 一种金属氧化物半导体（MOS）型半导体器件，包括硅衬底，第一阴极电极和耦合到硅衬底并位于硅衬底的远端上的第二阴极电极，多晶硅（Poly-Si ）栅极，其近端位于所述硅衬底之上并且位于所述第一阴极电极和所述第二阴极电极之间，其中所述多晶硅栅极包括相对于所述硅衬底正交延伸的第一柱，所述第一柱包括第一掺杂硅板， 涉及包括第二掺杂硅板的硅衬底，其中所述第二柱被定位成在所述第一柱和所述第二柱之间产生宽度，阳极电极，其耦合到所述第一柱和所述第二柱并且从所述第一柱和所述第二柱横向延伸; 后置到第二柱，以及设置在第一硅衬底和第二硅衬底之间的电介质层。

公开(公告)号：US20150301363A1

公开(公告)日：2015-10-22

申请号：US14689601

申请日：2015-04-17

Applicant: Futurewei Technologies, Inc.

Inventor： Hongmin Chen ,  Qianfan Xu ,  Li Yang ,  Xiao Shen ,  Dawei Zheng ,  Yusheng Bai ,  Hongbing Lei ,  Eric Dudley

IPC: G02F1/025 ,  H01L29/167 ,  G02B6/13 ,  H01L29/06 ,  H01L29/66 ,  H01L29/94 ,  H01L29/49 ,  H01L29/51

CPC classification number: G02F1/025 ,  G02B6/13 ,  G02B2006/12061 ,  G02B2006/12142 ,  G02F2001/0151 ,  H01L29/0649 ,  H01L29/167 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/518 ,  H01L29/66181 ,  H01L29/94

Abstract: A metal-oxide semiconductor (MOS) optical modulator including a doped semiconductor layer having a waveguide structure, a dielectric layer disposed over the waveguide structure of the doped semiconductor layer, a gate region disposed over the dielectric layer, wherein the gate region comprises a transparent electrically conductive material having a refractive index lower than that of silicon, and a metal contact disposed over the gate region. The metal contact, the gate region, and the waveguide structure of the doped semiconductor layer may be vertically aligned with each other.

Abstract translation: 一种金属氧化物半导体（MOS）光学调制器，包括具有波导结构的掺杂半导体层，设置在掺杂半导体层的波导结构之上的电介质层，设置在电介质层上的栅极区，其中栅极区包括透明 具有低于硅的折射率的导电材料和设置在栅极区域上的金属接触。 掺杂半导体层的金属接触，栅极区域和波导结构可以彼此垂直对准。

公开(公告)号：US10133098B2

公开(公告)日：2018-11-20

申请号：US14689601

申请日：2015-04-17

Applicant: Futurewei Technologies, Inc.

Inventor： Hongmin Chen ,  Qianfan Xu ,  Li Yang ,  Xiao Shen ,  Dawei Zheng ,  Yusheng Bai ,  Hongbing Lei ,  Eric Dudley

IPC: G02F1/025 ,  G02B6/13 ,  H01L29/94 ,  H01L29/06 ,  H01L29/167 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  G02B6/12 ,  G02F1/015

Abstract: A metal-oxide semiconductor (MOS) optical modulator including a doped semiconductor layer having a waveguide structure, a dielectric layer disposed over the waveguide structure of the doped semiconductor layer, a gate region disposed over the dielectric layer, wherein the gate region comprises a transparent electrically conductive material having a refractive index lower than that of silicon, and a metal contact disposed over the gate region. The metal contact, the gate region, and the waveguide structure of the doped semiconductor layer may be vertically aligned with each other.

公开(公告)号：US10097277B2

公开(公告)日：2018-10-09

申请号：US15414349

申请日：2017-01-24

Applicant: Futurewei Technologies, Inc.

Inventor： Xueyan Zheng ,  Jianying Zhou ,  Xiao Shen ,  Chunlei Liao ,  Hongbing Lei ,  Hongmin Chen ,  Yu Sheng Bai

IPC: H04B10/564 ,  H04B10/516 ,  H04B10/079 ,  H04L7/00

Abstract: An apparatus comprises: a first input tap; a first optical modulator coupled to the first input tap; a first output tap coupled to the first optical modulator so that the first optical modulator is positioned between the first input tap and the first output tap; and a controller indirectly coupled to the first input tap and the first output tap.

公开(公告)号：US20160204576A1

公开(公告)日：2016-07-14

申请号：US14962990

申请日：2015-12-08

Applicant: Futurewei Technologies, Inc.

Inventor： Hongmin Chen

IPC: H01S5/06 ,  H01S3/106 ,  H01S5/30 ,  H01S5/00

CPC classification number: H01S5/0612 ,  H01S3/1062 ,  H01S5/0014 ,  H01S5/1032 ,  H01S5/142 ,  H01S5/3013

Abstract: A laser comprises a gain medium, and a mirror coupled to the gain medium and comprising a coupler coupled to the gain medium, a phase section coupled to the coupler, a bandpass filter coupled to the phase section, and a comb reflector (CR) coupled to the bandpass filter. A laser chip package comprises a substrate, and a laser coupled to the substrate and comprising a filter comprising a first interferometer with a first transmittance, and a second interferometer with a second transmittance, wherein the filter is configured to provide a filter transmittance based on the first transmittance and the second transmittance, and a comb reflector (CR) coupled to the filter and comprising a ring with a circumference, and a refractive index, wherein the CR is configured to provide a CR reflectivity based on the circumference and the refractive index.

Abstract translation: 激光器包括增益介质和耦合到增益介质并包括耦合到增益介质的耦合器的镜子，耦合到耦合器的相位部分，耦合到相位部分的带通滤波器和耦合到梳状反射器（CR）的梳状反射器 到带通滤波器。 激光芯片封装包括衬底和耦合到衬底并包括具有第一透射率的第一干涉仪和具有第二透射率的第二干涉仪的滤光器的激光器，其中所述滤光器被配置为基于所述滤光器透射率 第一透射率和第二透射率，以及耦合到滤光器并包括具有圆周的环和折射率的梳状反射器（CR），其中CR被配置为基于圆周和折射率提供CR反射率。

公开(公告)号：US20150293303A1

公开(公告)日：2015-10-15

申请号：US14680917

申请日：2015-04-07

Applicant: Futurewei Technologies, Inc.

Inventor： Huapu Pan ,  Zongrong Liu ,  Hongzhen Wei ,  Hongmin Chen

IPC: G02B6/136 ,  G02B6/122 ,  G02B6/132 ,  G02B6/12

CPC classification number: G02B6/136 ,  G02B6/1223 ,  G02B6/132 ,  G02B6/305 ,  G02B2006/12061 ,  G02B2006/12097 ,  G02B2006/12195

Abstract: A method of fabricating an edge coupling device and an edge coupling device are provided. The method includes removing a portion of cladding material to form a trench over an inversely tapered silicon waveguide, depositing a material having a refractive index greater than silicon dioxide over remaining portions of the cladding material and in the trench, and removing a portion of the material within the trench to form a ridge waveguide.

Abstract translation: 提供一种制造边缘耦合装置和边缘耦合装置的方法。 该方法包括去除包层材料的一部分以在反锥形硅波导上形成沟槽，在包层材料的剩余部分和沟槽中沉积具有大于二氧化硅的折射率的材料，并且去除材料的一部分 在沟槽内形成脊形波导。

公开(公告)号：US20170045761A1

公开(公告)日：2017-02-16

申请号：US15336489

申请日：2016-10-27

Applicant: Futurewei Technologies, Inc.

Inventor： Qianfan Xu ,  Xiao Shen ,  Hongmin Chen

IPC: G02F1/025 ,  H01L29/66 ,  H01L29/94

CPC classification number: G02F1/025 ,  G02F2202/104 ,  G02F2202/105 ,  H01L29/66181 ,  H01L29/94

Abstract: A metal-oxide-semiconductor (MOS) type semiconductor device, comprising a silicon substrate, a first cathode electrode and a second cathode electrode coupled to the silicon substrate and located on distal ends of the silicon substrate, a poly-silicon (Poly-Si) gate proximally located above the silicon substrate and between the first cathode electrode and the second cathode electrode, wherein the Poly-Si gate comprises a first post extending orthogonally relative to the silicon substrate comprising a first doped silicon slab, a second post extending orthogonally relative to the silicon substrate comprising a second doped silicon slab, wherein the second post is positioned so as to create a width between the first post and the second post, an anode electrode coupled to the first post and the second post and extending laterally from the first post to the second post, and a dielectric layer disposed between the first silicon substrate and the second silicon substrate.

Abstract translation: 一种金属氧化物半导体（MOS）型半导体器件，包括硅衬底，第一阴极电极和耦合到硅衬底并位于硅衬底的远端上的第二阴极电极，多晶硅（Poly-Si ）栅极，其近端位于所述硅衬底之上并且位于所述第一阴极电极和所述第二阴极电极之间，其中所述多晶硅栅极包括相对于所述硅衬底正交延伸的第一柱，所述第一柱包括第一掺杂硅板， 涉及包括第二掺杂硅板的硅衬底，其中所述第二柱被定位成在所述第一柱和所述第二柱之间产生宽度，阳极电极，其耦合到所述第一柱和所述第二柱并且从所述第一柱和所述第二柱横向延伸; 后置到第二柱，以及设置在第一硅衬底和第二硅衬底之间的电介质层。

公开(公告)号：US09231361B2

公开(公告)日：2016-01-05

申请号：US14266248

申请日：2014-04-30

Applicant: Futurewei Technologies, Inc.

Inventor： Hongmin Chen ,  Xuejin Yan ,  Rongsheng Miao ,  Xiao Shen ,  Zongrong Liu

IPC: H01L21/00 ,  H01S3/042 ,  H01L21/311 ,  H01S5/026 ,  H01S5/042 ,  H01S5/06 ,  H01S5/0625 ,  H01S5/125 ,  H01S5/50 ,  G02B6/12

CPC classification number: H01S5/0612 ,  G02B2006/12176 ,  H01L21/311 ,  H01S3/042 ,  H01S5/02453 ,  H01S5/02461 ,  H01S5/0261 ,  H01S5/0425 ,  H01S5/06256 ,  H01S5/125 ,  H01S5/2086 ,  H01S5/209 ,  H01S5/2275 ,  H01S5/5045

Abstract: A monolithically integrated thermal tunable laser comprising a layered substrate comprising an upper surface and a lower surface, and a thermal tuning assembly comprising a heating element positioned on the upper surface, a waveguide layer positioned between the upper surface and the lower surface, and a thermal insulation layer positioned between the waveguide layer and the lower surface, wherein the thermal insulation layer is at least partially etched out of an Indium Phosphide (InP) sacrificial layer, and wherein the thermal insulation layer is positioned between Indium Gallium Arsenide (InGaAs) etch stop layers.

Abstract translation: 一种单片集成的热可调激光器，包括包括上表面和下表面的分层衬底，以及包括位于上表面上的加热元件的热​​调节组件，位于上表面和下表面之间的波导层，以及热 绝缘层位于所述波导层和所述下表面之间，其中所述绝热层至少部分地从磷化铟（InP）牺牲层蚀刻出去，并且其中所述绝热层位于砷化镓（InGaAs）蚀刻停止点之间 层。