公开(公告)号：JP2000106417A

公开(公告)日：2000-04-11

申请号：JP24474199

申请日：1999-08-31

Applicant: GEN ELECTRIC

Inventor： FILLION RAYMOND A ,  DAUM WOLFGANG ,  KOLC RONALD FRANK ,  KUK DONALD WILLIAM ,  WOJNAROWSKI ROBERT J

IPC: H01L25/18 ,  H01L21/58 ,  H01L21/60 ,  H01L23/538 ,  H01L25/04 ,  H01L25/065 ,  H01L23/522

Abstract: PROBLEM TO BE SOLVED: To be able to manufacture a compound MCM in a high yield and at a low cost by providing a first interconnection structure in which specific part bonding pads are mutually connected and a second interconnection structure in which specific sub-module bonding pads are mutually connected. SOLUTION: Part bonding pads 26, 28, 30 and 32 are mutually bonded by a first interconnection structure 50. This locates at the upper part of parts 22 and 24 and a substrate 38 and is the multi-layer interconnection structure 50 which is bonded with those by a bonding layer 52. Additionally, a patterned metallic layer 74 is formed on a dielectric cap layer 70 and at the inside of a through hole 72 to complete the interconnection structure. Further, the metallic layer 74 includes a sub-module bonding pad 76 locating on the first dielectric cap layer 70. Thus, the multi-layer interconnection structure 50 forms all internal wirings in the sub-module 20 and also forms the bonding pad 76 for bonding all outer blocks.

公开(公告)号：JP2002305199A

公开(公告)日：2002-10-18

申请号：JP2001382426

申请日：2001-12-17

Applicant: GEN ELECTRIC

Inventor： BURDICK WILLIAM EDWARD JR ,  ROSE JAMES WILSON ,  DUROCHER KEVIN MATTHEW ,  FILLION RAYMOND A

IPC: H01L23/52 ,  H01H20060101 ,  H01L21/3205 ,  H01L21/48 ,  H01L21/60 ,  H01L23/12 ,  H01L23/34 ,  H01L23/50 ,  H01L23/538 ,  H01P1/04 ,  H05K3/06 ,  H05K3/38

Abstract: PROBLEM TO BE SOLVED: To provide an electronic package, in which an opened window is arranged above a device active region and a wiring having a large number of pins is installed. SOLUTION: An interconnection structure includes a dielectric layer (10); a first metallization pattern (12) on the dielectric layer, the first metallization pattern including at least one etch stop having a perimeter (22) defined at least one etch stop opening (24); a cured adhesive (38) on a portion of the dielectric layer, the adhesive not being present in an area aligned with at least one etch stop; and at least one electrical device (16) being attached to the dielectric layer by the adhesive, such that the active area (20) of the at least one electrical device is aligned with the etch stop perimeter. The active area of the at least one electrical device may further be aligned with at least one predetermined area defined by an optical additional portion (150) of cured adhesive, the additional portion of the cured adhesive which is attached adhesively to the dielectric layer and not attached adhesively to at least one electrical device.