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    FINE-PITCH FLEXIBLE WIRING
    1.
    发明申请
    FINE-PITCH FLEXIBLE WIRING 审中-公开
    精细接线灵活接线

    公开(公告)号：WO2013181000A3

    公开(公告)日：2014-02-27

    申请号：PCT/US2013041750

    申请日：2013-05-20

    Applicant: GEN ELECTRIC

    Inventor： ROSE JAMES WILSON ,  NAGARKAR KAUSTUBH RAVINDRA ,  GALLIGAN CRAIG PATRICK ,  SHAH BINOY MILAN ,  ASTLEY OLIVER RICHARD

    IPC: H01L23/49

    CPC classification number: H01L24/43 ,  H01L24/46 ,  H01L2224/43 ,  H01L2224/85207 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H05K1/118 ,  H05K2203/0235 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

    Abstract: A flexible wire assembly (20) includes a plurality of elongated conductors (26) and insulators (24) each having a quadrilateral cross section (28) and alternatingly laminated together, the flexible wire assembly (20) having a wire width (ww) measured across the conductor (26) and insulators (24), a wire height (wh) equivalent to the height of the conductors (26) and insulators (24), and a wire length (wl) which is measured in a longitudinal direction orthogonal to the wire width (ww) and the wire height (wh), wherein the wire length (wl) is one or more orders of magnitude greater than the wire width(ww) and the wire height (wh); and a first device (25) comprising a plurality of bond pads (27) spaced to define a bond pad (27) pitch, wherein the flexible wire assembly (20) is coupled to the first device (25) at the bond pads (27) such that spacing of the conductor conductors (26) is matched to the bond pad (27) pitch.

    Abstract translation: 柔性电线组件（20）包括多个细长导体（26）和绝缘体（24），每个具有四边形横截面（28）并交替层压在一起，柔性电线组件（20）具有测量的电线宽度（ww） 穿过导体（26）和绝缘体（24），与导体（26）和绝缘体（24）的高度相当的导线高度（wh），以及在纵向方向上测量的导线长度（w1） 线宽（ww）和线高（wh），其中线长（w1）比线宽（ww）和线高（wh）大一个或多个数量级; 以及第一装置（25），其包括间隔开以限定接合垫（27）间距的多个接合焊盘（27），其中所述柔性线组件（20）在所述接合焊盘（27）处联接到所述第一装置（25） ），使得导体导体（26）的间隔与接合焊盘（27）的间距相匹配。

    INTERCONNECTION METHOD AND STRUCTURE THEREOF
    3.
    发明专利
    INTERCONNECTION METHOD AND STRUCTURE THEREOF 审中-公开

    公开(公告)号：JP2002305199A

    公开(公告)日：2002-10-18

    申请号：JP2001382426

    申请日：2001-12-17

    Applicant: GEN ELECTRIC

    Inventor： BURDICK WILLIAM EDWARD JR ,  ROSE JAMES WILSON ,  DUROCHER KEVIN MATTHEW ,  FILLION RAYMOND A

    IPC: H01L23/52 ,  H01H20060101 ,  H01L21/3205 ,  H01L21/48 ,  H01L21/60 ,  H01L23/12 ,  H01L23/34 ,  H01L23/50 ,  H01L23/538 ,  H01P1/04 ,  H05K3/06 ,  H05K3/38

    Abstract: PROBLEM TO BE SOLVED: To provide an electronic package, in which an opened window is arranged above a device active region and a wiring having a large number of pins is installed. SOLUTION: An interconnection structure includes a dielectric layer (10); a first metallization pattern (12) on the dielectric layer, the first metallization pattern including at least one etch stop having a perimeter (22) defined at least one etch stop opening (24); a cured adhesive (38) on a portion of the dielectric layer, the adhesive not being present in an area aligned with at least one etch stop; and at least one electrical device (16) being attached to the dielectric layer by the adhesive, such that the active area (20) of the at least one electrical device is aligned with the etch stop perimeter. The active area of the at least one electrical device may further be aligned with at least one predetermined area defined by an optical additional portion (150) of cured adhesive, the additional portion of the cured adhesive which is attached adhesively to the dielectric layer and not attached adhesively to at least one electrical device.

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