公开(公告)号：WO1992006490A1

公开(公告)日：1992-04-16

申请号：PCT/US1991007339

申请日：1991-10-02

Applicant: GENERAL ELECTRIC COMPANY

Inventor： GENERAL ELECTRIC COMPANY ,  WEI, Ching-Yeu ,  POSSIN, George, Edward ,  KWASNICK, Robert, Forrest

IPC: H01L21/28

CPC classification number: H01L29/66765 ,  H01L21/28008 ,  H01L29/42384 ,  H01L29/78669

Abstract: A self-aligned, inverted, thin film field effect transistor is produced by patterning the gate electrode (18) to have tapered edge followed by conformal deposition of subsequent layers of the device structure up through a support layer (30) followed by deposition of a subordinate layer (such as the source/drain metallizatio (34,36)) on the support layer. The subordinate layer itself may be a planarization or non-conformal layer or may have a subsequent non-conformal planarization layer (40) disposed thereon. Thereafter, the structure is non-selectively etched (preferably reactive ion etched) until the support layer is exposed by the creation of an aperture in the subordinate layer in alignment with raised portions of the reference layer while leaving the subordinate layer present on other parts of the structure. Thereafter, the remainder of the device is fabricated with the source and drain electrodes (34, 36) self-aligned with respect to the gate conductor (18) using a selective etch method.

公开(公告)号：WO1992006505A1

公开(公告)日：1992-04-16

申请号：PCT/US1991007338

申请日：1991-10-02

Applicant: GENERAL ELECTRIC COMPANY

Inventor： GENERAL ELECTRIC COMPANY ,  KWASNICK, Robert, Forrest ,  POSSIN, George, Edward ,  HOLDEN, David, Eugene ,  SAIA, Richard, Joseph

IPC: H01L29/784

CPC classification number: H01L29/66765 ,  H01L21/32139 ,  H01L29/458

Abstract: Minimum line spacing is reduced and line spacing uniformity is increased in thin film transistors by employing source/drain metallization having a first relatively thin layer of a first conductor and a second relatively thick layer of a second conductor. The second conductor is selected to be one which may be preferentially etched in the presence of the first conductor whereby the first conductor acts as an etch stop for the etchant used to pattern the second conductor portion of the source/drain metallization. This etching is preferably done using dry etching. Dry etching typically provides substantially better control of line width than wet etching. The etching of the second conductor can be done with a dry etch process which etches the photoresist at substantially the same rate as the second conductor whereby the second conductor is provided with a sidewall slope of substantially 45 DEG which improves the quality of passivation provided by subsequent deposition of a conformal passivating layer.

Abstract translation: 通过采用具有第一相对薄的第一导体层和第二相对较厚的第二导体层的源极/漏极金属化，薄膜晶体管中的最小线间距减小，并且线间隔均匀性增加。 第二导体被选择为可以在第一导体存在的情况下优先蚀刻的导体，由此第一导体充当用于图案化源极/漏极金属化的第二导体部分的蚀刻剂的蚀刻停止。 该蚀刻优选使用干蚀刻进行。 干蚀刻通常比湿式蚀刻提供对线宽度的更好的控制。 第二导体的蚀刻可以通过干法蚀刻工艺进行，该蚀刻工艺以基本上与第二导体相同的速率蚀刻光致抗蚀剂，由此第二导体设置有大致为45°的侧壁斜率，这提高了后续提供的钝化质量 共形钝化层的沉积。

公开(公告)号：WO1992006504A1

公开(公告)日：1992-04-16

申请号：PCT/US1991007340

申请日：1991-10-02

Applicant: GENERAL ELECTRIC COMPANY

Inventor： GENERAL ELECTRIC COMPANY ,  KWASNICK, Robert, Forrest ,  WEI, Ching-Yeu

IPC: H01L29/60

CPC classification number: H01L29/66765 ,  H01L21/28008 ,  H01L29/42384 ,  H01L29/4908

Abstract: A thin film transistor includes a two-layer gate metallization comprising a relatively thin first layer of a first conductor and a relatively thick second layer of a second conductor with the second conductor being capable of being etched with an etchant that produces substantially no etching of the first conductor layer. During device fabrication, the thick gate metallization layer (second conductor) is selectively etched until all of that material is removed in the openings in the mask. The thin lower layer (first conductor) is then etched with a minimum of etching into the substrate. The gate dielectric and subsequent layers deposited over this gate metallization have high integrity and highly reliable continuity because of the sloped nature of the gate metallization sidewalls, and because of the shallow gate metallization topography due to minimization of substrate etching during gate metallization patterning.

公开(公告)号：WO1992006497A1

公开(公告)日：1992-04-16

申请号：PCT/US1991007335

申请日：1991-10-02

Applicant: GENERAL ELECTRIC COMPANY

Inventor： GENERAL ELECTRIC COMPANY ,  WEI, Ching-Yeu ,  POSSIN, George, Edward ,  KWASNICK, Robert, Forrest

IPC: H01L27/01

CPC classification number: H01L29/66765 ,  H01L21/28008 ,  H01L29/42384 ,  H01L29/4908

Abstract: Positive control over the length of the overlap between the gate electrode (18) and the source and drain electrodes (36) in a thin film transistor is provided by a gate conductor layer (18) comprising two different conductors (14, 16) having differing etching characteristics. As part of the gate conductor pattern definition process, both gate conductors (14, 16) are etched to expose the underlying material (12) and the upper gate conductor layer (16) is etched back to expose the first gate conductor layer (14) in accordance with the desired overlap between the gate electrode (18) and the source and drain electrodes (36). Thereafter, the remainder of the device is fabricated with the source and drain electrodes (36) self-aligned with respect to the second gate conductor layer (14) using a planarization and non-selective etch method.

公开(公告)号：WO2003022017A3

公开(公告)日：2003-03-13

申请号：PCT/US2002/026651

申请日：2002-08-21

Applicant: GENERAL ELECTRIC COMPANY

Inventor： EBERHARD, Jeffrey, Wayne ,  COLE, Herbert, Stanley ,  KWASNICK, Robert, Forrest ,  SITNIK-NIETERS, Theresa, Ann

IPC: H05G1/00

Abstract: A radiation imaging system (20) comprising a scintillator (26), an imager array (30), and a lamination layer (22). Lamination layer (22) bonds and optically couples scintillator (26) to imager array (30). Lamination layer (22) is comprised of a lamination material that is substantially free from void spaces. Radiation imaging system (20) fabrication comprises the steps of disposing lamination layer (22) between a light imager (24) and a scintillator (26) to form a subassembly (150). Light imager (24) comprises imager array (30), an imaging plate surface (34) and a plurality of contact pads (32). Additional steps include subjecting subassembly (150) to a vacuum; heating subassembly (150) to a bonding temperature, exerting a bonding force on subassembly (150), maintaining the vacuum, the bonding temperature and the bonding force until light imager (24) is bonded to the scintillator (26) and the lamination layer (22) is comprised of lamination material that is substantially free from void spaces.

公开(公告)号：WO2003022017A2

公开(公告)日：2003-03-13

申请号：PCT/US2002/026651

申请日：2002-08-21

Applicant: GENERAL ELECTRIC COMPANY

Inventor： EBERHARD, Jeffrey, Wayne ,  COLE, Herbert, Stanley ,  KWASNICK, Robert, Forrest ,  SITNIK-NIETERS, Theresa, Ann

IPC: H05G1/00

CPC classification number: G01T1/2002 ,  G01T1/1642 ,  G01T1/2018 ,  Y10T156/10

Abstract: A radiation imaging system (20) comprising a scintillator (26), an imager array (30), and a lamination layer (22). Lamination layer (22) bonds and optically couples scintillator (26) to imager array (30). Lamination layer (22) is comprised of a lamination material that is substantially free from void spaces. Radiation imaging system (20) fabrication comprises the steps of disposing lamination layer (22) between a light imager (24) and a scintillator (26) to form a subassembly (150). Light imager (24) comprises imager array (30), an imaging plate surface (34) and a plurality of contact pads (32). Additional steps include subjecting subassembly (150) to a vacuum; heating subassembly (150) to a bonding temperature, exerting a bonding force on subassembly (150), maintaining the vacuum, the bonding temperature and the bonding force until light imager (24) is bonded to the scintillator (26) and the lamination layer (22) is comprised of lamination material that is substantially free from void spaces.

Abstract translation: 一种包括闪烁体（26），成像器阵列（30）和层压层（22）的辐射成像系统（20）。 层叠层（22）将闪烁体（26）光学耦合到成像器阵列（30）。 层压层（22）由基本上没有空隙的层压材料构成。 辐射成像系统（20）制造包括以下步骤：在光成像仪（24）和闪烁体（26）之间设置层压层（22）以形成子组件（150）。 光成像仪（24）包括成像器阵列（30），成像板表面（34）和多个接触焊盘（32）。 附加步骤包括使组件（150）经受真空; 加热组件（150）到接合温度，在子组件（150）上施加结合力，保持真空，接合温度和接合力，直到光成像仪（24）结合到闪烁体（26）和层压层 22）由基本上没有空隙的层压材料构成。

公开(公告)号：WO1994020982A1

公开(公告)日：1994-09-15

申请号：PCT/US1994001737

申请日：1994-02-24

Applicant: GENERAL ELECTRIC COMPANY

Inventor： GENERAL ELECTRIC COMPANY ,  POSSIN, George, Edward ,  KWASNICK, Robert, Forrest

IPC: H01L21/336

CPC classification number: H01L29/66765 ,  H01L21/0274 ,  Y10S148/10 ,  Y10S148/102 ,  Y10S148/105

Abstract: A thin-film field-effect transistor is fabricated by forming an electrically insulative island (23) between the source and the drain. A cap (61) is formed on the island with a brim that overhangs the island. A layer of source-drain metal (64, 65), which will subsequently constitute the source and drain contacts, is then deposited upon the source, the drain, and the cap (61), but the overhang creates an exposed region which can be attacked by an etchant. When the etchant is applied, it etches away the cap (61), thereby lifting off the source-drain metal (64, 65) which coated the cap, leaving the fully formed source and drain contacts separated by the island.

Abstract translation: 通过在源极和漏极之间形成电绝缘岛（23）来制造薄膜场效应晶体管。 在岛上形成一个帽（61），其上有一个悬垂在岛上的边缘。 随后将构成源极和漏极接触的源极 - 漏极金属层（64,65）沉积在源极，漏极和帽（61）上，但是突出部形成暴露的区域，该区域可以是 被腐蚀剂攻击。 当施加蚀刻剂时，其蚀刻掉盖（61），从而提起涂覆盖的源极 - 漏极金属（64,65），留下由岛隔开的完全形成的源极和漏极接触。

公开(公告)号：WO1995017767A1

公开(公告)日：1995-06-29

申请号：PCT/US1994014530

申请日：1994-12-15

Applicant: GENERAL ELECTRIC COMPANY

Inventor： GENERAL ELECTRIC COMPANY ,  WEI, Ching-Yeu ,  SALISBURY, Roger, Stephen ,  KWASNICK, Robert, Forrest

IPC: H01L21/768

CPC classification number: H01L27/146 ,  G02F2001/136263 ,  H01L21/76892 ,  H01L23/525 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Repair lines in an imager device include protective layers disposed over steps in the repair lines where the repair lines extend over underlying components in the imager array. The protective layers each include a layer of polyimide to provide protection for the step portions of the conductive repair line from etchants and the like to which the conductive line is exposed during fabrication processes for the imager array. The protective layers are disposed over the steps of a conductive line in a repair crossover region so as to provide a repair area free from the protective material of the protective layers disposed thereon in the repair crossover region where the conductive repair line is disposed in vertical alignment with an underlying address line.

Abstract translation: 成像设备中的修复线包括设置在修复线上的步骤之上的保护层，其中修复线延伸到成像器阵列中的下面的部件上。 保护层各自包括聚酰亚胺层，以在导电修复线的台阶部分与蚀刻剂等保护，该蚀刻剂等在成像器阵列的制造工艺期间暴露导电线。 保护层设置在修复交叉区域中的导电线的台阶上，以便提供修复区域，该修复区域不设置在修复交叉区域中的保护层的保护材料，其中导电修复线设置成垂直对齐 与底层地址行。

公开(公告)号：WO1992006502A1

公开(公告)日：1992-04-16

申请号：PCT/US1991007336

申请日：1991-10-02

Applicant: GENERAL ELECTRIC COMPANY

Inventor： GENERAL ELECTRIC COMPANY ,  KWASNICK, Robert, Forrest

IPC: H01L27/146

CPC classification number: H01L27/14643

Abstract: An improved structure for a thin film transistor photodiode photosensitive array retains the semiconductor material of the thin film transistor layer under the entire area occupied by the photosensitive device for each pixel of the array. This eliminates a step in the layer on which the source metallization of the thin film transistor is disposed and results in more reliable passivation of that layer and thereby increases yield and reduces cost. Several improved processes may be employed for the fabrication of such a thin film transistor photodiode photosensitive array.

Abstract translation: 用于薄膜晶体管光电二极管光敏阵列的改进的结构将薄膜晶体管层的半导体材料保持在阵列的每个像素的光敏器件占据的整个区域之下。 这消除了在其上设置薄膜晶体管的源金属化的层中的步骤，并且导致该层的更可靠的钝化，从而提高了产量并降低了成本。 可以采用几种改进的方法来制造这种薄膜晶体管光电二极管光敏阵列。

公开(公告)号：WO1992006501A2

公开(公告)日：1992-04-16

申请号：PCT/US1991007146

申请日：1991-09-27

Applicant: GENERAL ELECTRIC COMPANY

Inventor： GENERAL ELECTRIC COMPANY ,  KINGSLEY, Jack, Dean ,  KWASNICK, Robert, Forrest ,  WEI, Ching-Yeu ,  SAIA, Richard, Joseph

IPC: H01L27/14

CPC classification number: H01L27/14663

Abstract: A radiation imager includes a photodetector array having topographically patterned surface features, which include support islands disposed over the active portion of one or more photodetectors in the photodetector array. A structured scintillator array having individual columnar scintillator elements is disposed in fixed relation to the photodetector array so that the individual scintillator elements are disposed on scintillator support islands. A barrier layer is disposed between the support islands and the photodetector array to minimize chemical interactions between the material forming the support island and the underlying photodetector array during the fabrication process. After the support islands have been patterned, the scintillator elements are grown by selectively depositing scintillator material on the support islands.