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公开(公告)号：US12293994B2
公开(公告)日：2025-05-06
申请号：US17955225
申请日：2022-09-28
Applicant: GlobalFoundries U.S. Inc.
Inventor： Vvss Satyasuresh Choppalli , Anupam Dutta , Rajendran Krishnasamy , Robert Gauthier, Jr. , Xiang Xiang Lu , Anindya Nath
IPC: H01L25/07 , H01L21/77 , H01L23/14 , H01L23/522
Abstract: Structures including multiple semiconductor devices and methods of forming same. The structure comprises a first device structure including a first well and a second well in a semiconductor substrate, a second device structure including a doped region in the semiconductor substrate, and a first high-resistivity region in the semiconductor substrate. The first well has a first conductivity type, the second well has a second conductivity type opposite to the first conductivity type, and the first well adjoins the second well to define a p-n junction. The doped region of the second device structure has the first conductivity type or the second conductivity type. The high-resistivity region has a higher electrical resistivity than the semiconductor substrate, and the high-resistivity region is positioned between the first device structure and the second device structure.
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公开(公告)号：US20240105683A1
公开(公告)日：2024-03-28
申请号：US17955225
申请日：2022-09-28
Applicant: GlobalFoundries U.S. Inc.
Inventor： Vvss Satyasuresh Choppalli , Anupam Dutta , Rajendran Krishnasamy , Robert Gauthier, JR. , Xiang Xiang Lu , Anindya Nath
IPC: H01L25/07 , H01L21/77 , H01L23/14 , H01L23/522
CPC classification number: H01L25/072 , H01L21/77 , H01L23/147 , H01L23/5228
Abstract: Structures including multiple semiconductor devices and methods of forming same. The structure comprises a first device structure including a first well and a second well in a semiconductor substrate, a second device structure including a doped region in the semiconductor substrate, and a first high-resistivity region in the semiconductor substrate. The first well has a first conductivity type, the second well has a second conductivity type opposite to the first conductivity type, and the first well adjoins the second well to define a p-n junction. The doped region of the second device structure has the first conductivity type or the second conductivity type. The high-resistivity region has a higher electrical resistivity than the semiconductor substrate, and the high-resistivity region is positioned between the first device structure and the second device structure.
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公开(公告)号：US20230420551A1
公开(公告)日：2023-12-28
申请号：US17849867
申请日：2022-06-27
Applicant: GlobalFoundries U.S. Inc.
Inventor： Shesh Mani Pandey , Souvick Mitra , Anindya Nath
IPC: H01L29/745 , H01L29/66
CPC classification number: H01L29/7455 , H01L29/66363
Abstract: Structures for a silicon-controlled rectifier and methods of forming a structure for a silicon-controlled rectifier. The structure comprises a semiconductor substrate, a dielectric layer on the semiconductor substrate, and a first well and a second well in the semiconductor substrate beneath the dielectric layer. The first well has a first conductivity type, the second well has a second conductivity type opposite to the first conductivity type, and the second well adjoins the first well along a p-n junction. The structure further comprises a first terminal and a second terminal above the dielectric layer, a first connection extending through the dielectric layer from the first terminal to the first well, and a second connection extending through the dielectric layer from the second terminal to the second well.
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公开(公告)号：US20230369314A1
公开(公告)日：2023-11-16
申请号：US17662921
申请日：2022-05-11
Applicant: GlobalFoundries U.S. Inc.
Inventor： Robert J. Gauthier, JR. , Rajendran Krishnasamy , Anupam Dutta , Anindya Nath , Xiangxiang Lu , Satyasuresh Vvss Choppalli , Lin Lin
IPC: H01L27/02
CPC classification number: H01L27/0262 , H01L27/0266
Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure with resistive semiconductor material for a back well. The IC structure may include a semiconductor substrate having a deep well, and a device within a first portion of the deep well. The device includes a first doped semiconductor material coupled to a first contact, and a second doped semiconductor material coupled to a second contact. The deep well couples the first doped semiconductor material to the second doped semiconductor material. A first back well is within a second portion of the deep well. A first resistive semiconductor material is within the deep well and defines a boundary between the first portion of the deep well and the second portion of the deep well.
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公开(公告)号：US11430881B2
公开(公告)日：2022-08-30
申请号：US16810076
申请日：2020-03-05
Applicant: GLOBALFOUNDRIES U.S. INC.
Inventor： Anindya Nath , Alain F. Loiseau
Abstract: The present disclosure relates to a polysilicon-diode triggered compact silicon controlled rectifier. In particular, the present disclosure relates to a structure including a silicon controlled rectifier (SCR) which includes an n-well adjacent and in direct contact with a p-well, the SCR includes at least one shallow trench isolation (STI) region, and at least one polysilicon diode on top of the at least one STI region.
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Patent Agency Ranking
公开(公告)号：US12191300B2
公开(公告)日：2025-01-07
申请号：US17662921
申请日：2022-05-11
Applicant: GlobalFoundries U.S. Inc.
Inventor： Robert J. Gauthier, Jr. , Rajendran Krishnasamy , Anupam Dutta , Anindya Nath , Xiangxiang Lu , Satyasuresh Vvss Choppalli , Lin Lin
IPC: H01L27/02
Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure with resistive semiconductor material for a back well. The IC structure may include a semiconductor substrate having a deep well, and a device within a first portion of the deep well. The device includes a first doped semiconductor material coupled to a first contact, and a second doped semiconductor material coupled to a second contact. The deep well couples the first doped semiconductor material to the second doped semiconductor material. A first back well is within a second portion of the deep well. A first resistive semiconductor material is within the deep well and defines a boundary between the first portion of the deep well and the second portion of the deep well.
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公开(公告)号：US20240072038A1
公开(公告)日：2024-02-29
申请号：US17895153
申请日：2022-08-25
Applicant: GlobalFoundries U.S. Inc.
Inventor： Anindya Nath , Alain F. Loiseau , Robert J. Gauthier, JR. , Souvick Mitra
IPC: H01L27/02 , H01L21/763
CPC classification number: H01L27/0262 , H01L21/763
Abstract: Embodiments of the disclosure provide a semiconductor controlled rectifier (SCR) structure and methods to form the same. The SCR structure may include a first polycrystalline semiconductor material on a first insulator and includes a first well therein. A monocrystalline semiconductor material is adjacent the first polycrystalline semiconductor material and includes an anode region and a cathode region therein. A second polycrystalline semiconductor material is on a second insulator and includes a second well therein.
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公开(公告)号：US11855074B2
公开(公告)日：2023-12-26
申请号：US17170325
申请日：2021-02-08
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor： Zhiqing Li , William J. Taylor, Jr. , Anindya Nath
IPC: H01L27/02
CPC classification number: H01L27/0262
Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge devices and methods of manufacture. The structure includes: a plurality of regions of a first dopant type; insulator material separating each region of the plurality of regions of the first dopant type; and a substrate contacting the plurality of regions of the first dopant type, the substrate comprising a base region of a second dopant type different than the first dopant type and an outer segment surrounding the plurality of regions of the first dopant type, the outer segment comprises an electrical resistivity higher than the second dopant type.
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公开(公告)号：US11658480B2
公开(公告)日：2023-05-23
申请号：US17068967
申请日：2020-10-13
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor： Anindya Nath , Zhiqing Li , Souvick Mitra , Alain Loiseau , Wei Liang
CPC classification number: H02H9/046 , H01L27/0248 , H01L27/0262 , H01L27/0266
Abstract: Embodiments of the disclosure provide an electrostatic discharge (ESD) device, including: an input pad; an underlapped field effect transistor (UL-FET) with a trigger voltage Vt, including: an underlapped drain region coupled to the input pad; a source region coupled to ground; and a gate structure coupled to the input pad; and a blocking layer separating the underlapped drain region from the gate structure of the UL-FET by an underlap distance.
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公开(公告)号：US20240290776A1
公开(公告)日：2024-08-29
申请号：US18173313
申请日：2023-02-23
Applicant: GlobalFoundries U.S. Inc.
Inventor： Anindya Nath , Rajendran Krishnasamy , Robert J. Gauthier, JR.
CPC classification number: H01L27/0262 , H01L29/87
Abstract: Embodiments of the disclosure provide a structure including a semiconductor substrate. The semiconductor substrate includes a porous semiconductor region, the porous semiconductor region including a cavity. The cavity includes a semiconductor layer therein. The porous semiconductor further includes a device. The device includes a first well at least partially in the semiconductor layer and a second well at least partially in the semiconductor layer and positioned laterally immediately adjacent the first well. The device further includes a first doped region abutting the first well; and a second doped region abutting the second well, wherein the first well and the second doped region have a first type conductivity and the second well and the first doped region having a second type conductivity that is different from the first type conductivity.
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