公开(公告)号：US20250120156A1

公开(公告)日：2025-04-10

申请号：US18378312

申请日：2023-10-10

Applicant: GlobalFoundries U.S. Inc.

Inventor： Brett T. Cucci ,  Jacob M. DeAngelis ,  Spencer H. Porter ,  Trevor S. Wills ,  Mark D. Levy

IPC: H01L29/40 ,  H01L29/20 ,  H01L29/66 ,  H01L29/778

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to high electron mobility transistors and methods of manufacture. The structure includes: a semiconductor substrate; a gate structure on the semiconductor substrate; a gate metal connecting to the gate structure; and a field plate connected to a source region of the gate structure. The gate metal and the field plate include a same material.

公开(公告)号：US11881506B2

公开(公告)日：2024-01-23

申请号：US17386062

申请日：2021-07-27

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Johnatan A. Kantarovsky ,  Mark D. Levy ,  Brett T. Cucci ,  Jeonghyun Hwang ,  Siva P. Adusumilli

IPC: H01L29/06 ,  H01L29/778 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/0649 ,  H01L21/823481 ,  H01L29/66431 ,  H01L29/7786

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to gate structures and methods of manufacture. The structure includes: a gate structure comprising a horizontal portion and a substantially vertical stem portion; and an air gap surrounding the substantially vertical stem portion and having a curved surface under the horizontal portion.

公开(公告)号：US20230139011A1

公开(公告)日：2023-05-04

申请号：US17517738

申请日：2021-11-03

Applicant: GlobalFoundries U.S. Inc.

Inventor： Zhong-Xiang He ,  Jeonghyun Hwang ,  Ramsey M. Hazbun ,  Brett T. Cucci ,  Ajay Raman ,  Johnatan A. Kantarovsky

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/40 ,  H01L29/778 ,  H01L29/423

Abstract: Disclosed are embodiments of a transistor (e.g., a III-V high electron mobility transistor (HEMT), a III-V metal-insulator-semiconductor HEMT (MISHEMT), or the like) that has multiple self-aligned terminals. The self-aligned terminals include a self-aligned gate, a self-aligned source terminal and, optionally, a self-aligned drain terminal. By forming self-aligned terminals during processing, the separation distances between the terminals (e.g., between the gate and source terminal and, optionally, between the gate and drain terminal) can be reduced in order to reduce device size and to improve performance (e.g., to reduce on resistance and increase switching speeds). Also disclosed herein are method embodiments for forming such a transistor.

公开(公告)号：US20250140599A1

公开(公告)日：2025-05-01

申请号：US18385268

申请日：2023-10-30

Applicant: GlobalFoundries U.S. Inc.

Inventor： Jacob M. DeAngelis ,  Trevor S. Wills ,  Mark D. Levy ,  Spencer H. Porter ,  Brett T. Cucci ,  Rajendran Krishnasamy

IPC: H01L21/762 ,  H01L29/04 ,  H01L29/778

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to devices with isolation structures and methods of manufacture. The structure includes: a stack of semiconductor materials; a semiconductor substrate under the stack of semiconductor materials; a trench filled with in insulator material; and a damaged region of the stack of semiconductor materials extending from at least a bottom of the insulator material to the semiconductor substrate.

公开(公告)号：US20240210621A1

公开(公告)日：2024-06-27

申请号：US18597173

申请日：2024-03-06

Applicant: GlobalFoundries U.S. Inc.

Inventor： Brett T. Cucci ,  Yusheng Bian ,  Abdelsalam Aboketaf ,  Edward W. Kiewra

IPC: G02B6/122 ,  G02B6/12 ,  G02B6/125 ,  G02B6/132

CPC classification number: G02B6/1228 ,  G02B6/1223 ,  G02B6/125 ,  G02B6/132 ,  G02B2006/12061 ,  G02B2006/12147 ,  G02B6/1225

Abstract: Disclosed are embodiments of a photonic integrated circuit (PIC) structure with a waveguide core having tapered sidewall liner(s) (e.g., symmetric tapered sidewall liners on opposing sides of a waveguide core, asymmetric tapered sidewall liners on opposing sides of a waveguide core, or a tapered sidewall liner on one side of a waveguide core). In some embodiments, the tapered sidewall liner(s) and waveguide core have different refractive indices. In an exemplary embodiment, the waveguide core is a first material (e.g., silicon) and the tapered sidewall liner(s) is/are a second material (e.g., silicon nitride) with a smaller refractive index than the first material. In another exemplary embodiment, the waveguide core is a first compound and the tapered sidewall liner(s) is/are a second compound with the same elements (e.g., silicon and nitrogen) as the first compound but with a smaller refractive index. Also disclosed are method embodiments for forming such a PIC structure.

公开(公告)号：US20230037420A1

公开(公告)日：2023-02-09

申请号：US17386062

申请日：2021-07-27

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Johnatan A. Kantarovsky ,  Mark D. Levy ,  Brett T. Cucci ,  Jeonghyun Hwang ,  Siva P. Adusumilli

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/778

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to gate structures and methods of manufacture. The structure includes: a gate structure comprising a horizontal portion and a substantially vertical stem portion; and an air gap surrounding the substantially vertical stem portion and having a curved surface under the horizontal portion.

公开(公告)号：US11916119B2

公开(公告)日：2024-02-27

申请号：US17517738

申请日：2021-11-03

Applicant: GlobalFoundries U.S. Inc.

Inventor： Zhong-Xiang He ,  Jeonghyun Hwang ,  Ramsey M. Hazbun ,  Brett T. Cucci ,  Ajay Raman ,  Johnatan A. Kantarovsky

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/423 ,  H01L29/40 ,  H01L29/778

CPC classification number: H01L29/41783 ,  H01L29/401 ,  H01L29/42376 ,  H01L29/6656 ,  H01L29/66462 ,  H01L29/66553 ,  H01L29/7786

Abstract: Disclosed are embodiments of a transistor (e.g., a III-V high electron mobility transistor (HEMT), a III-V metal-insulator-semiconductor HEMT (MISHEMT), or the like) that has multiple self-aligned terminals. The self-aligned terminals include a self-aligned gate, a self-aligned source terminal and, optionally, a self-aligned drain terminal. By forming self-aligned terminals during processing, the separation distances between the terminals (e.g., between the gate and source terminal and, optionally, between the gate and drain terminal) can be reduced in order to reduce device size and to improve performance (e.g., to reduce on resistance and increase switching speeds). Also disclosed herein are method embodiments for forming such a transistor.

公开(公告)号：US11823948B2

公开(公告)日：2023-11-21

申请号：US17696348

申请日：2022-03-16

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Uzma Rana ,  Anthony K. Stamper ,  Steven M. Shank ,  Brett T. Cucci

IPC: H01L27/00 ,  H01L21/76 ,  H01L27/06 ,  H01L21/762

CPC classification number: H01L21/76 ,  H01L21/762 ,  H01L27/0617

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to bulk wafer switch isolation structures and methods of manufacture. The structure includes: a bulk substrate material; an active region on the bulk substrate material; an inactive region adjacent to the active region; and an amorphous material covering the bulk substrate material in the inactive region, which is adjacent to the active region.

公开(公告)号：US11764258B2

公开(公告)日：2023-09-19

申请号：US17108543

申请日：2020-12-01

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Brett T. Cucci ,  Siva P. Adusumilli ,  Johnatan A. Kantarovsky ,  Claire E. Kardos ,  Sen Liu

IPC: H01L29/06 ,  H01L21/768 ,  H01L21/764

CPC classification number: H01L29/0649 ,  H01L21/764 ,  H01L21/7682

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to airgap isolation structures and methods of manufacture. The structure includes: a bulk substrate material; a first airgap isolation structure in the bulk substrate material and having a first aspect ratio; and a second airgap isolation structure in the bulk substrate material and having a second aspect ratio different from the first aspect ratio.

公开(公告)号：US11322387B1

公开(公告)日：2022-05-03

申请号：US17069098

申请日：2020-10-13

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Uzma Rana ,  Anthony K. Stamper ,  Steven M. Shank ,  Brett T. Cucci

IPC: H01L27/00 ,  H01L21/76 ,  H01L21/26 ,  H01L27/06 ,  H01L21/762

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to bulk wafer switch isolation structures and methods of manufacture. The structure includes: a bulk substrate material; an active region on the bulk substrate material; an inactive region adjacent to the active region; and an amorphous material covering the bulk substrate material in the inactive region, which is adjacent to the active region.