公开(公告)号：US20240222356A1

公开(公告)日：2024-07-04

申请号：US18149279

申请日：2023-01-03

Applicant: GlobalFoundries U.S. Inc.

Inventor： James P. Mazza ,  Jia Zeng ,  Xuelian Zhu ,  Navneet K. Jain ,  Mahbub Rashed ,  Jacob Mazza

IPC: H01L27/02

CPC classification number: H01L27/0207

Abstract: A multi-row standard cell and an integrated circuit (IC) structure using the standard cell are provided. The IC structure includes a plurality of cell rows extending in a first direction. At least two cell rows of the plurality of cell rows have different row heights. The IC structure includes a multi-row standard cell positioned in two or more cell rows having different row heights. At least one active region is shared by portions of the multi-row cell across the at least two cell rows. The IC structure may also include one or more asymmetric shared power rails disposed in an asymmetric manner across a row boundary between the at least two cell rows of different row heights. The multi-row standard cells and IC structures allow placement of multi-row cells for mixed track height arrangements in a manner not limited to multiples of row heights.

公开(公告)号：US11205648B2

公开(公告)日：2021-12-21

申请号：US16866663

申请日：2020-05-05

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anton V. Tokranov ,  James P. Mazza ,  Elizabeth A. Strehlow ,  Harold Mendoza ,  Jay A. Mody ,  Clynn J. Mathew ,  Hong Yu ,  Yea-Sen Lin

IPC: H01L27/088 ,  H01L29/36 ,  H01L29/78 ,  H01L27/06 ,  H01L29/66 ,  H01L21/8234

Abstract: An integrated circuit (IC) structure with a single active region having a doping profile different than that of a set of active regions, is disclosed. The IC structure provides a single active region, e.g., a fin, on a substrate with a first doping profile, and a set of active regions, e.g., fins, electrically isolated from the single active region on the substrate. The set of active regions have a second doping profile that is different than the first doping profile of the single active region. For example, the second doping profile can have a deeper penetration into the substrate than the first doping profile.

公开(公告)号：US20240313113A1

公开(公告)日：2024-09-19

申请号：US18182926

申请日：2023-03-13

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anton V. Tokranov ,  James P. Mazza ,  Eric Scott Kozarsky ,  Elizabeth A. Strehlow ,  Vitor A. Vulcano Rossi ,  Hong Yu

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/66

CPC classification number: H01L29/7846 ,  H01L21/76229 ,  H01L29/66795 ,  H01L29/7851

Abstract: Disclosed is a semiconductor structure and method of forming the semiconductor structure. Specifically, the semiconductor structure can include a first semiconductor fin extending from a semiconductor substrate. The semiconductor structure can further include an isolation region on the semiconductor substrate adjacent to a lower portion of the first semiconductor fin. The first semiconductor fin can, for example, be incorporated into a single-fin fin-type semiconductor device, such as a single-fin fin-type field effect transistor (FINFET). The isolation region can include at least one shallow trench isolation (STI) structure positioned laterally between and immediately adjacent to sections of a deep trench isolation (DTI) structure. With this alternating DTI-STI-DTI configuration, overall shrinkage of isolation material of the isolation region during anneals is reduced and, thus, so are stress-induced crystalline defects in the first semiconductor fin. Also disclosed are methods for forming such a semiconductor structure.

公开(公告)号：US20240021621A1

公开(公告)日：2024-01-18

申请号：US17812790

申请日：2022-07-15

Applicant: GlobalFoundries U.S. Inc.

Inventor： James P. Mazza ,  Xuelian Zhu ,  Jia Zeng, JR. ,  Navneet Jain ,  Mahbub Rashed

IPC: H01L27/118 ,  H01L27/02

CPC classification number: H01L27/11807 ,  H01L27/0207 ,  H01L2027/11875 ,  H01L2027/11881

Abstract: An integrated circuit (IC) structure includes a plurality of cell rows with each cell row including a plurality of (standard) cells. A power rail for at least one pair of adjacent cell rows is asymmetric relative to a cell boundary between adjacent cells of the at least one pair of adjacent cell rows. Embodiments of the disclosure can also include the standard cell including a plurality of transistors at a device layer, and at least a portion of an isolation area at an edge of the device layer defining a cell boundary. The standard cell also includes the power rail including a first portion within the cell boundary and a second portion outside the cell boundary. The first portion and the second portion have different heights such that the power rail is asymmetric across the cell boundary. The asymmetric power rail provides seamless integration of cell libraries having different heights.

公开(公告)号：US12046651B2

公开(公告)日：2024-07-23

申请号：US17515914

申请日：2021-11-01

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： James P. Mazza ,  Elizabeth Strehlow ,  Motoi Ichihashi ,  Xuelian Zhu ,  Jia Zeng

IPC: H01L27/02 ,  H01L23/528 ,  H01L29/423

CPC classification number: H01L29/42376 ,  H01L23/5286

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a logic cell layout design for high density transistors and methods of manufacture. The structure includes a plurality of active gates in a high density transistor, and at least one dummy gate which is continuous and is adjacent to at least one active gate of the active gates in a multi-row cell of the high density transistor.

公开(公告)号：US11913971B2

公开(公告)日：2024-02-27

申请号：US17183432

申请日：2021-02-24

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Romain H. A. Feuillette ,  David C. Pritchard ,  Elizabeth Strehlow ,  James P. Mazza

IPC: G01P15/00 ,  G01C9/24 ,  G01C9/06 ,  G01C9/20 ,  G01P15/18 ,  G01C9/18

CPC classification number: G01P15/006 ,  G01C9/06 ,  G01C9/20 ,  G01C9/24 ,  G01P15/18 ,  G01C2009/182

Abstract: Disclosed are a motion-sensitive field effect transistor (MSFET), a motion detection system, and a method. The MSFET includes a gate structure with a reservoir containing conductive fluid and gate electrode(s). Given position(s) of the gate electrode(s) and a fill level of the fluid within the reservoir, contact between the gate electrode(s) and the fluid depends upon the orientation the MSFET channel region relative to the top surface of the conductive fluid and the orientation of the MSFET channel region relative to the top surface of the conductive fluid depends upon position in space and/or movement of the MSFET and, particularly, position in space and/or movement of the chip on which the MSFET is formed. An electrical property of the MSFET in response to specific bias conditions varies depending on whether or not or to what extent the gate electrode(s) contact the fluid and is, thus, measurable for sensing chip motion.

公开(公告)号：US20220268805A1

公开(公告)日：2022-08-25

申请号：US17183432

申请日：2021-02-24

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Romain H.A. Feuillette ,  David C. Pritchard ,  Elizabeth Strehlow ,  James P. Mazza

IPC: G01P15/00

Abstract: Disclosed are a motion-sensitive field effect transistor (MSFET), a motion detection system, and a method. The MSFET includes a gate structure with a reservoir containing conductive fluid and gate electrode(s). Given position(s) of the gate electrode(s) and a fill level of the fluid within the reservoir, contact between the gate electrode(s) and the fluid depends upon the orientation the MSFET channel region relative to the top surface of the conductive fluid and the orientation of the MSFET channel region relative to the top surface of the conductive fluid depends upon position in space and/or movement of the MSFET and, particularly, position in space and/or movement of the chip on which the MSFET is formed. An electrical property of the MSFET in response to specific bias conditions varies depending on whether or not or to what extent the gate electrode(s) contact the fluid and is, thus, measurable for sensing chip motion.

公开(公告)号：US20210351283A1

公开(公告)日：2021-11-11

申请号：US16866663

申请日：2020-05-05

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anton V. Tokranov ,  James P. Mazza ,  Elizabeth A. Strehlow ,  Harold Mendoza ,  Jay A. Mody ,  Clynn J. Mathew ,  Hong Yu ,  Yea-Sen Lin

IPC: H01L29/66 ,  H01L29/10 ,  H01L27/06 ,  H01L27/088

Abstract: An integrated circuit (IC) structure with a single active region having a doping profile different than that of a set of active regions, is disclosed. The IC structure provides a single active region, e.g., a fin, on a substrate with a first doping profile, and a set of active regions, e.g., fins, electrically isolated from the single active region on the substrate. The set of active regions have a second doping profile that is different than the first doping profile of the single active region. For example, the second doping profile can have a deeper penetration into the substrate than the first doping profile.

公开(公告)号：US20240387668A1

公开(公告)日：2024-11-21

申请号：US18199054

申请日：2023-05-18

Applicant: GlobalFoundries U.S. Inc.

Inventor： Hong Yu ,  David C. Pritchard ,  Navneet K. Jain ,  James P. Mazza ,  Romain H. A. Feuillette

IPC: H01L29/423 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/775

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to nanosheet transistor structures with tunable channels and inner sidewall spacers and methods of manufacture. The structure includes: a plurality of stacked semiconductor nanosheets over a semiconductor substrate; a plurality of gate structures surrounding individual nanosheets of the plurality of semiconductor nanosheets, with a lower gate structure comprising a length at least equal to a length of each remaining gate structure of the plurality of gate structures; an inner sidewall spacer adjacent each of the plurality of gate structures; and source/drain regions on opposing sides of the plurality of gate structures, separated therefrom by the inner sidewall spacer.

公开(公告)号：US20240347638A1

公开(公告)日：2024-10-17

申请号：US18301382

申请日：2023-04-17

Applicant: GlobalFoundries U.S. Inc.

Inventor： Navneet K. Jain ,  David Charles Pritchard ,  Romain H.A. Feuillette ,  James P. Mazza ,  Hong Yu

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/10 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/28123 ,  H01L29/1037 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/66795

Abstract: Disclosed are a structure including a fin-type field effect transistor (FINFET) and a method. The FINFET includes first and second fins. An isolation structure is adjacent the outer sidewall of the first fin at a channel region and, optionally, fills a groove in the outer sidewall so the fin width is reduced. A gate is adjacent the inner sidewall of the first fin at the channel region and extends over the first fin to the isolation structure. The gate is further adjacent an inner sidewall and top of the second fin at a channel region. In some embodiments, a second isolation structure is adjacent an outer sidewall of the second fin at the channel region and, optionally, fills a groove in the outer sidewall so the fin width is reduced. In this case, the gate extends over the second fin to the second isolation structure.