公开(公告)号：US11837605B2

公开(公告)日：2023-12-05

申请号：US17644858

申请日：2021-12-17

Applicant: GlobalFoundries U.S. Inc.

Inventor： Tom Herrmann ,  Zhixing Zhao ,  Alban Zaka ,  Yiching Chen

IPC: H01L27/12 ,  H01L21/84 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L29/0653 ,  H01L29/7838

Abstract: A structure including a semiconductor-on-insulator (SOI) substrate. The SOI substrate includes an SOI layer over a buried insulator layer over a base semiconductor layer. The structure includes a high-voltage first field effect transistor (FET) adjacent to a high performance, low voltage second FET. The high voltage FET has a gate electrode on the buried insulator layer, and a source and a drain in the base semiconductor layer under the buried insulator layer. Hence, the buried insulator layer operates as a gate dielectric for the high voltage FET. The low voltage FET has a source and a drain over the buried insulator layer, i.e., in the SOI layer. A trench isolation is in each of the source and the drain of the first, high voltage FET. The source of the high voltage FET surrounds the trench isolation therein.

公开(公告)号：US20250133735A1

公开(公告)日：2025-04-24

申请号：US18489672

申请日：2023-10-18

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Nicki Nico MIKA ,  Tom Herrmann ,  Thomas Melde

IPC: H10B41/30 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788

Abstract: A non-volatile memory structure includes a semiconductor substrate and first and second memory devices on the semiconductor substrate. Each of the first and second memory devices includes a floating gate, a tunnelling insulator under the floating gate, an isolation layer over the floating gate, and at least one of a select gate and a control gate over the isolation layer. The non-volatile memory structure further includes an erase gate shared by the first and second memory devices, a source region under the erase gate, and a shallow trench isolation structure between the erase gate and the source region. The shallow trench isolation structure increases the number of write/erase cycles that can be performed by the non-volatile memory structure.

公开(公告)号：US11245032B2

公开(公告)日：2022-02-08

申请号：US16373620

申请日：2019-04-02

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Ignasi Cortes ,  Alban Zaka ,  Tom Herrmann ,  El Mehdi Bazizi ,  Richard Francis Taylor, III

IPC: H01L29/78 ,  H01L29/786 ,  H01L29/66

Abstract: The present disclosure relates generally to semiconductor structures, and more particularly to asymmetric field effect transistors (FET) on fully depleted silicon on insulator (FDSOI) semiconductor devices for high frequency and high voltage applications and their method of manufacture. The semiconductor device of the present disclosure includes a semiconductor-on-insulator (SOI) layer disposed above a substrate, the SOI layer having a source region, a channel region, a drift region and a drain region, where the drift region adjoins the drain region and the channel region, a gate structure disposed on the channel region, a multilayer drain spacer disposed on a drain-facing sidewall of the gate structure and covering the drift region, and a source spacer disposed on a source-facing sidewall of the gate structure, where the source and drain spacers are asymmetric with each other.

公开(公告)号：US20240055434A1

公开(公告)日：2024-02-15

申请号：US18493081

申请日：2023-10-24

Applicant: GlobalFoundries U.S. Inc.

Inventor： Tom Herrmann ,  Zhixing Zhao ,  Alban Zaka ,  Yiching Chen

IPC: H01L27/12 ,  H01L21/84 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L29/7838 ,  H01L29/0653

Abstract: A structure including a semiconductor-on-insulator (SOI) substrate including a semiconductor-on-insulator (SOI) layer over a buried insulator layer over a base semiconductor layer. The structure further includes a first field effect transistor (FET) adjacent to a second FET, the first FET having a gate electrode on the buried insulator layer and a source and a drain in the base semiconductor layer under the buried insulator layer. The second FET has a source and a drain over the buried insulator layer. The structure further includes a trench isolation in each of the source and the drain of the first FET, the source of the first FET surrounding the trench isolation therein and the drain of the first FET surrounding the trench isolation therein.

公开(公告)号：US20230197731A1

公开(公告)日：2023-06-22

申请号：US17644858

申请日：2021-12-17

Applicant: GlobalFoundries U.S. Inc.

Inventor： Tom Herrmann ,  Zhixing Zhao ,  Alban Zaka ,  Yiching Chen

IPC: H01L27/12 ,  H01L29/06 ,  H01L29/78 ,  H01L21/84

CPC classification number: H01L27/1203 ,  H01L29/0653 ,  H01L29/7838 ,  H01L21/84

Abstract: A structure including a semiconductor-on-insulator (SOI) substrate. The SOI substrate includes an SOI layer over a buried insulator layer over a base semiconductor layer. The structure includes a high-voltage first field effect transistor (FET) adjacent to a high performance, low voltage second FET. The high voltage FET has a gate electrode on the buried insulator layer, and a source and a drain in the base semiconductor layer under the buried insulator layer. Hence, the buried insulator layer operates as a gate dielectric for the high voltage FET. The low voltage FET has a source and a drain over the buried insulator layer, i.e., in the SOI layer. A trench isolation is in each of the source and the drain of the first, high voltage FET. The source of the high voltage FET surrounds the trench isolation therein.

公开(公告)号：US20240170576A1

公开(公告)日：2024-05-23

申请号：US18056754

申请日：2022-11-18

Applicant: GlobalFoundries U.S. Inc.

Inventor： Zhixing Zhao ,  Tom Herrmann ,  Jegadheesan Venkatesan

IPC: H01L29/78 ,  H01L27/12

CPC classification number: H01L29/7838 ,  H01L27/1203 ,  H01L29/7831

Abstract: Embodiments of the disclosure provide a structure with a back-gate having oppositely doped semiconductor regions. The structure may include a transistor over a substrate. The transistor includes a gate structure having a gate length. A back-gate region is within the substrate below the gate structure of the transistor. The back-gate region includes a pair of doped semiconductor regions with a P-N junction therebetween. Each of the pair of semiconductor materials has a length extending substantially in parallel with respect to the gate length.

公开(公告)号：US11929433B2

公开(公告)日：2024-03-12

申请号：US17454481

申请日：2021-11-10

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ignasi Cortes ,  Alban Zaka ,  Tom Herrmann ,  El Mehdi Bazizi ,  Richard Francis Taylor, III

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/7835 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/78603 ,  H01L29/78624

Abstract: The present disclosure relates generally to semiconductor structures, and more particularly to asymmetric field effect transistors (FET) on fully depleted silicon on insulator (FDSOI) semiconductor devices for high frequency and high voltage applications and their method of manufacture. The semiconductor device of the present disclosure includes a semiconductor-on-insulator (SOI) layer disposed above a substrate, the SOI layer having a source region, a channel region, a drift region and a drain region, where the drift region adjoins the drain region and the channel region, a gate structure disposed on the channel region, a multilayer drain spacer disposed on a drain-facing sidewall of the gate structure and covering the drift region, and a source spacer disposed on a source-facing sidewall of the gate structure, where the source and drain spacers are asymmetric with each other.