公开(公告)号：EP4386755A1

公开(公告)日：2024-06-19

申请号：EP23197838.8

申请日：2023-09-18

Applicant: GlobalFoundries U.S. Inc.

Inventor： Parvarandeh, Pirooz ,  Gopinath, Venkatesh P. ,  Jain, Navneet ,  Paul, Bipul C. ,  Mulaosmanovic, Halid

IPC: G11C14/00

CPC classification number: G11C14/0072

Abstract: Structures for a static random access memory bit cell and methods of forming a structure for a static random access memory bit cell. The structure comprises a static random access memory bit cell including a first node and a second node, a first ferroelectric field-effect transistor including a first terminal connected to the first node, and a second ferroelectric field-effect transistor including a second terminal connected to the second node.

公开(公告)号：EP4387410A1

公开(公告)日：2024-06-19

申请号：EP23197413.0

申请日：2023-09-14

Applicant: GlobalFoundries U.S. Inc.

Inventor： Gopinath, Venkatesh P. ,  Jain, Navneet ,  Ren, Hongru ,  Derrickson, Alexander ,  Peng, Jianwei ,  Paul, Bipul C.

IPC: H10B63/00 ,  H10N70/20 ,  H01L27/12

CPC classification number: H10N70/20 ,  H01L27/1259 ,  H10B63/30 ,  H10B63/80 ,  H10N70/826 ,  H10N70/8833 ,  H01L27/1222 ,  G11C2213/7920130101 ,  G11C2213/7420130101 ,  G11C13/003 ,  G11C11/1659

Abstract: Structures that include field-effect transistors and methods of forming such structures. The structure comprises a substrate, a dielectric layer on the substrate, a first field-effect transistor including a first semiconductor layer over the dielectric layer and a first gate electrode, and a second field-effect transistor including a second semiconductor layer over the dielectric layer and a second gate electrode adjacent to the first gate electrode. The second semiconductor layer is connected to the first semiconductor layer, and the first and second semiconductor layers are positioned between the first gate electrode and the second gate electrode.

公开(公告)号：EP4557290A1

公开(公告)日：2025-05-21

申请号：EP24175901.8

申请日：2024-05-15

Applicant: GlobalFoundries U.S. Inc.

Inventor： Jain, Navneet ,  Rashed, Mahbub

IPC: G11C11/417

Abstract: A disclosed memory structure includes memory cells connected to first and second cell supply voltage lines. A programming circuit enables programming of a low cell supply voltage (Vcsl) on the first cell supply voltage line and includes transistors with different threshold voltages connected to ground and further connectable, via switches, to the first cell supply voltage line. The programming circuit can further include an additional switch connected between ground and the first cell supply voltage line. In an operational mode, the first cell supply voltage line is discharged to ground via the additional switch. In the retention mode, one of the transistors of the programming circuit is connected by a corresponding switch to the first cell supply voltage line for programming of Vcsl. Optionally, the memory structure can be implemented in FDSOI and the transistors of the programming circuit can also be back biased for fine tuning of Vcsl.