公开(公告)号：EP4398299A1

公开(公告)日：2024-07-10

申请号：EP23195592.3

申请日：2023-09-06

Applicant: GlobalFoundries U.S. Inc.

Inventor： Mazza, James P. ,  Zeng, Jia ,  Zhu, Xuelian ,  Jain, Navneet K. ,  Rashed, Mahbub ,  Mazza, Jacob

IPC: H01L27/02 ,  G06F30/392 ,  H01L27/118

CPC classification number: H01L27/0207 ,  H01L2027/1187520130101 ,  G06F30/392 ,  H01L2027/1188120130101

Abstract: A multi-row standard cell and an integrated circuit (IC) structure using the standard cell are provided. The IC structure includes a plurality of cell rows extending in a first direction. At least two cell rows of the plurality of cell rows have different row heights. The IC structure includes a multi-row standard cell positioned in two or more cell rows having different row heights. At least one active region is shared by portions of the multi-row cell across the at least two cell rows. The IC structure may also include one or more asymmetric shared power rails disposed in an asymmetric manner across a row boundary between the at least two cell rows of different row heights. The multi-row standard cells and IC structures allow placement of multi-row cells for mixed track height arrangements in a manner not limited to multiples of row heights.

公开(公告)号：EP4557290A1

公开(公告)日：2025-05-21

申请号：EP24175901.8

申请日：2024-05-15

Applicant: GlobalFoundries U.S. Inc.

Inventor： Jain, Navneet ,  Rashed, Mahbub

IPC: G11C11/417

Abstract: A disclosed memory structure includes memory cells connected to first and second cell supply voltage lines. A programming circuit enables programming of a low cell supply voltage (Vcsl) on the first cell supply voltage line and includes transistors with different threshold voltages connected to ground and further connectable, via switches, to the first cell supply voltage line. The programming circuit can further include an additional switch connected between ground and the first cell supply voltage line. In an operational mode, the first cell supply voltage line is discharged to ground via the additional switch. In the retention mode, one of the transistors of the programming circuit is connected by a corresponding switch to the first cell supply voltage line for programming of Vcsl. Optionally, the memory structure can be implemented in FDSOI and the transistors of the programming circuit can also be back biased for fine tuning of Vcsl.

公开(公告)号：EP4535425A1

公开(公告)日：2025-04-09

申请号：EP24168621.1

申请日：2024-04-05

Applicant: GlobalFoundries U.S. Inc.

Inventor： Kim, Juhan ,  Parihar, Sanjay Rai ,  Rashed, Mahbub ,  Alpaslan, Zahir Yilmaz

IPC: H01L27/02 ,  G09G3/36 ,  H10B10/00 ,  H01L27/12

Abstract: Disclosed are a pixel and a compact memory-in-pixel display (e.g., implemented in a fully-depleted semiconductor-on-insulator processing technology platform). A block of electronic components for a pixel includes a memory cell array, a driving circuit for an LED, and a logic circuit connected between the memory cell array and driving circuit. The memory cell array is above a Pwell, the driving circuit is above an adjacent Nwell, and the logic circuit includes P-type transistors on the Nwell and N-type transistors on the Pwell. A pixel array is above alternating P and N wells with a single buried Nwell below. Specifically, each column of pixels is above adjacent elongated P and N wells and, within each column, adjacent pixels have mirrored layouts. Furthermore, adjacent columns of pixels are above two elongated wells of one type and a shared elongated well of the opposite type therebetween and the adjacent columns have mirrored layouts.

公开(公告)号：EP4535414A1

公开(公告)日：2025-04-09

申请号：EP24168619.5

申请日：2024-04-05

Applicant: GlobalFoundries U.S. Inc.

Inventor： Jain, Navneet K. ,  Kim, Juhan ,  Rashed, Mahbub

IPC: H01L21/84 ,  H01L27/12 ,  H01L27/092

Abstract: Disclosed is a fully depleted semiconductor-on-insulator structure including a buried Nwell in a substrate below P-type and N-type well regions, an insulator layer on the substrate, and mixed threshold voltage transistors on the insulator layer above at least one of the well regions. An Nwell can be connected to receive a positive bias voltage with any NFET and any PFET above being a FBB LVT/SLVT NFET and a RBB RVT/HVT PFET, respectively. A Pwell can be connected to receive another positive bias voltage less than the positive bias voltage on the Nwell with any NFET and any PFET above being a FBB RVT/HVT NFET and a RBB LVT/SLVT PFET, respectively. Additionally, or alternatively, a Pwell can be connected to receive a negative bias voltage with any NFET and any PFET above being a RBB RVT/HVT NFET and a FBB LVT/SLVT PFET, respectively.