公开(公告)号：US20250070781A1

公开(公告)日：2025-02-27

申请号：US18455669

申请日：2023-08-25

Applicant: GlobalFoundries U.S. Inc.

Inventor： Santosh Sharma ,  Mei Yu Soh

IPC: H03K19/003 ,  H03K17/0412

Abstract: Disclosed circuit structure embodiments include an enhancement mode transistor and a turn-off slew rate controller for automatically adding drain-source capacitance to the transistors when the transistor is transitioning to an off state. The added drain-source capacitance slows the turn-off slew rate (dV/dt_off) of the transistor without also increasing the turn-off energy loss (E_off). In some embodiments, the slew rate controller includes: sensors connected to the drain region for sensing both the drain voltage and the slew rate, respectively; a logic circuit for generating and outputting an enable signal based on output voltages from the sensors; and a capacitance adder for adding to the drain-source capacitance only when the logic value of the enable signal indicates that the drain voltage is at or above a predetermined positive drain voltage level and the slew rate is positive.

公开(公告)号：US12294364B2

公开(公告)日：2025-05-06

申请号：US18455669

申请日：2023-08-25

Applicant: GlobalFoundries U.S. Inc.

Inventor： Santosh Sharma ,  Mei Yu Soh

IPC: H03K19/003 ,  H03K17/0412 ,  H03K17/06

Abstract: A circuit structure includes an enhancement mode transistor and a turn-off slew rate controller for automatically adding drain-source capacitance to the transistor when the transistor is transitioning to an off state. The added drain-source capacitance slows the turn-off slew rate (dV/dt_off) of the transistor without also increasing the turn-off energy loss (E_off). The slew rate controller can include: sensors connected to the drain region for sensing both the drain voltage and the slew rate, respectively; a logic circuit for generating and outputting an enable signal based on output voltages from the sensors; and a capacitance adder for adding to the drain-source capacitance only when the logic value of the enable signal indicates that the drain voltage is at or above a predetermined positive drain voltage level and the slew rate is positive.

公开(公告)号：US20240275385A1

公开(公告)日：2024-08-15

申请号：US18167279

申请日：2023-02-10

Applicant: GlobalFoundries U.S. Inc.

Inventor： Santosh SHARMA ,  Mei Yu Soh

IPC: H03K19/0185 ,  H03K17/10 ,  H03K17/687 ,  H03K19/00 ,  H03K19/017

CPC classification number: H03K19/018535 ,  H03K17/102 ,  H03K17/6871 ,  H03K19/0013 ,  H03K19/01721

Abstract: A GaN logic circuit may include an input node receiving an input voltage, a first pull up transistor pulling up an output voltage in response to the input voltage, and a first depletion mode transistor having a first gate to which a first gate voltage is applied and a second gate to which a second gate voltage is applied. The first depletion mode transistor may control the first pull up transistor in response to a gate voltage difference between the first gate voltage and the second gate voltage. The logic device may further include a capacitor having a first end coupled to the first depletion mode transistor and a second end coupled to the first pull up transistor.