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公开(公告)号:US10180888B2
公开(公告)日:2019-01-15
申请号:US14912130
申请日:2013-09-27
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor: Melvin K Benedict , Eric L Pope , Andrew C. Walton
Abstract: Example implementations relate to using a spare memory on a memory module. In example implementations, a memory module may have a plurality of memories, including default memories and a spare memory. A plurality of data buffers on the memory module may select data nibbles from the plurality of memories such that when a default memory is identified as defective, a data nibble is selected from the spare memory and not from the defective default memory. A data nibble selected from the default memory may be in a first position in an output of the memory module when the default memory is functional. A data nibble selected from the spare memory may be in a second position in the output of the memory module.
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公开(公告)号:US10579115B2
公开(公告)日:2020-03-03
申请号:US16139109
申请日:2018-09-24
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor: Thomas Robert Bowden , Alan B Doerr , John Franz , Melvin K Benedict , Joseph Allen , John Norton , Binh Nguyen
IPC: G06F1/20 , G06F1/18 , H01L23/367 , H01L23/40 , G06F13/42
Abstract: A thermal management assembly in accordance with one example may include a first thermal management member that includes a first main region that is continuous, a first connection region that is discontinuous, and a first top side. The thermal management assembly may also include a second thermal management member that includes a second main region, a second connection region, and a second top side. The second main region and the second connection region are continuous. The thermal management assembly may further include a connection member to couple the first thermal management member and the second thermal management member to a memory device via the first connection region and the second connection region. The first top side and the second top side are substantially level with a top side of the memory device in a horizontal direction when the first thermal management member and the second thermal management member are coupled to the memory device.
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公开(公告)号:US09972941B2
公开(公告)日:2018-05-15
申请号:US15106655
申请日:2014-01-29
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor: Melvin K Benedict , Stephen F Contreras
IPC: H01R12/00 , H01R13/6471 , H01R12/52 , H01R12/72 , H01R12/73
CPC classification number: H01R13/6471 , H01R12/52 , H01R12/721 , H01R12/737
Abstract: A memory module connector (100) is described herein. The memory module connector (100) comprises a plurality of connector pins (102) distributed into a plurality of columns (104). The plurality of connector pins (102) further comprises a plurality of ground pins (106) for providing electrical ground to the memory module connector (100) and a plurality of signal pins (108) for carrying data signals across the memory module connector (100). Further, for each signal pin (108) provided in a column (104), each connector pin (102) adjacent to the signal pin (108) in an adjacent column (104) is a ground pin (106).
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公开(公告)号:US20170005438A1
公开(公告)日:2017-01-05
申请号:US15106655
申请日:2014-01-29
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor: Melvin K Benedict , Stephen F Contreras
IPC: H01R13/6471 , H01R12/73
CPC classification number: H01R13/6471 , H01R12/52 , H01R12/721 , H01R12/737
Abstract: A memory module connector (100) is described herein. The memory module connector (100) comprises a plurality of connector pins (102) distributed into a plurality of columns (104). The plurality of connector pins (102) further comprises a plurality of ground pins (106) for providing electrical ground to the memory module connector (100) and a plurality of signal pins (108) for carrying data signals across the memory module connector (100). Further, for each signal pin (108) provided in a column (104), each connector pin (102) adjacent to the signal pin (108) in an adjacent column (104) is a ground pin (106).
Abstract translation: 本文描述了存储器模块连接器(100)。 存储器模块连接器(100)包括分配到多个列(104)中的多个连接器引脚(102)。 多个连接器引脚(102)还包括用于向存储器模块连接器(100)提供电接地的多个接地引脚(106)和用于在存储器模块连接器(100)上承载数据信号的多个信号引脚(108) )。 此外,对于设置在列(104)中的每个信号引脚(108),与相邻列(104)中的信号引脚(108)相邻的每个连接器引脚(102)是接地引脚(106)。
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公开(公告)号:US20160203065A1
公开(公告)日:2016-07-14
申请号:US14912130
申请日:2013-09-27
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor: Melvin K Benedict , Eric L Pope , Andrew C. Walton
CPC classification number: G06F11/2038 , G06F3/0619 , G06F3/0656 , G06F3/0683 , G06F11/1016 , G06F11/1446 , G06F11/2058 , G06F11/2069 , G06F2201/84 , G11C7/1012 , G11C7/1033 , G11C29/846
Abstract: Example implementations relate to using a spare memory on a memory module. In example implementations, a memory module may have a plurality of memories, including default memories and a spare memory. A plurality of data buffers on the memory module may select data nibbles from the plurality of memories such that when a default memory is identified as defective, a data nibble is selected from the spare memory and not from the defective default memory. A data nibble selected from the default memory may be in a first position in an output of the memory module when the default memory is functional. A data nibble selected from the spare memory may be in a second position in the output of the memory module.
Abstract translation: 示例实现涉及在存储器模块上使用备用存储器。 在示例实现中,存储器模块可以具有多个存储器,包括默认存储器和备用存储器。 存储器模块上的多个数据缓冲器可以从多个存储器中选择数据半字节,使得当将默认存储器识别为有缺陷时,从备用存储器中选择数据半字节,而不是从缺陷的默认存储器中选择数据半字节。 当默认存储器功能时,从默认存储器中选择的数据半字节可以处于存储器模块的输出中的第一位置。 从备用存储器中选择的数据半字节可以处于存储器模块的输出中的第二位置。
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公开(公告)号:US10136544B2
公开(公告)日:2018-11-20
申请号:US15315380
申请日:2014-07-08
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor: John Norton , Melvin K Benedict , John P Franz
IPC: H01R12/00 , H05K7/14 , H05K7/20 , H01R12/73 , H01R13/629
Abstract: A dual in-line memory module (DIMM) connector can include a double data rate fourth generation (DDR4) DIMM connector to connect to a DIMM via a lowest notch of the DIMM relative to an electronic component on which the DIMM is located.
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公开(公告)号:US10068661B2
公开(公告)日:2018-09-04
申请号:US15913916
申请日:2018-03-06
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor: Lidia Warnes , Melvin K Benedict , Andrew C Walton
CPC classification number: G11C29/70 , G11C5/04 , G11C5/148 , G11C11/005 , G11C14/0018 , G11C29/44 , G11C29/808 , G11C29/835 , G11C2029/0409 , G11C2029/4402
Abstract: Example implementations relate to post package repair (PPR) data in non-volatile memory. In example implementations, PPR data may be stored in non-volatile memory on a memory module. PPR data may indicate how many PPRs have been performed on the memory module.
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公开(公告)号:US10725689B2
公开(公告)日:2020-07-28
申请号:US15752250
申请日:2015-08-28
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor: Melvin K Benedict , Eric L Pope
Abstract: In one example in accordance with the present disclosure, a system for backup of a physical memory region of volatile memory. The system may include: a non-volatile memory, a volatile memory, at least one processor to: execute an application that indicates a virtual memory region stored in the volatile memory, wherein the virtual memory region is associated with an application, determine a corresponding physical memory region of the volatile memory for backup based on the indicated virtual memory region, and at least one memory controller to: receive a backup signal for the physical memory region of the volatile memory, and responsive to receiving the backup signal, backup up the physical memory region of the volatile memory to a memory region of the non-volatile memory.
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公开(公告)号:US10453516B2
公开(公告)日:2019-10-22
申请号:US15899514
申请日:2018-02-20
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor: Reza M Bacchus , Melvin K Benedict , Stephen F Contreras , Eric L Pope , Chi K Sides , Chun-Pin Huang
IPC: G11C5/06 , G11C5/10 , G11C11/4074 , G11C5/14 , G11C5/04
Abstract: An example device in accordance with an aspect of the present disclosure includes a memory module having a voltage regulator module (VRM) to receive input power and deliver output power to components of the memory module at a first power plane. A sufficient number of stitching capacitors are to couple the first power plane to a second power plane.
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公开(公告)号:US10114433B2
公开(公告)日:2018-10-30
申请号:US15120511
申请日:2014-04-30
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor: Thomas Robert Bowden , Allen B Doerr , John Franz , Melvin K Benedict , Joseph Allen , John Norton , Binh Nguyen
Abstract: A thermal management assembly in accordance with one example may include a first thermal management member that includes a first main region that is continuous, a first connection region that is discontinuous, and a first top side. The thermal management assembly may also include a second thermal management member that includes a second main region, a second connection region, and a second top side. The second main region and the second connection region are continuous. The thermal management assembly may further include a connection member to couple the first thermal management member and the second thermal management member to a memory device via the first connection region and the second connection region. The first top side and the second top side are substantially level with a top side of the memory device in a horizontal direction when the first thermal management member and the second thermal management member are coupled to the memory device.
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