公开(公告)号：WO1998027486A1

公开(公告)日：1998-06-25

申请号：PCT/US1997022814

申请日：1997-12-12

Applicant: HEWLETT-PACKARD COMPANY

Inventor： HEWLETT-PACKARD COMPANY ,  FARABOSCHI, Paolo ,  FISHER, Joseph, A.

IPC: G06F09/38

CPC classification number: G06F9/3808 ,  G06F9/30152 ,  G06F9/30178 ,  G06F9/3816 ,  G06F9/3822 ,  G06F9/3885

Abstract: Method and apparatus for storing and expanding wide instruction words in a computer system are provided. The computer system includes a memory and an instruction cache. Compressed instruction words of a program are stored in a code heap segment of the memory, and code pointers are stored in a code pointer segment of the memory. Each of the code pointers contains a pointer to one of the compressed instruction words. Part of the program is stored in the instruction cache as expanded instruction words. During execution of the program, an instruction word is accessed in the instruction cache. When the instruction word required for execution is not present in the instruction cache, thereby indicating a cache miss, a code pointer corresponding to the required instruction word is accessed in the code pointer segment of memory. The code pointer is used to access a compressed instruction word corresponding to the required instruction word in the code heap segment of memory. The compressed instruction word is expanded to provide an expanded instruction word, which is loaded into the instruction cache and is accessed for execution.

Abstract translation: 提供了用于在计算机系统中存储和扩展宽指令字的方法和装置。 计算机系统包括存储器和指令高速缓存。 程序的压缩指令字存储在存储器的代码堆段中，代码指针存储在存储器的代码指针段中。 每个代码指针包含指向一个压缩指令字的指针。 程序的一部分作为扩展指令字存储在指令缓存中。 在程序执行期间，指令缓存中存取指令字。 当指令高速缓存中不存在执行所需的指令字，从而指示高速缓存未命中时，在存储器的代码指针段中访问与所需指令字对应的代码指针。 代码指针用于访问与存储器的代码堆段中所需指令字相对应的压缩指令字。 压缩指令字被扩展以提供扩展指令字，其被加载到指令高速缓存中并被访问以执行。

公开(公告)号：WO1998027485A1

公开(公告)日：1998-06-25

申请号：PCT/US1997022643

申请日：1997-12-12

Applicant: HEWLETT-PACKARD COMPANY

Inventor： HEWLETT-PACKARD COMPANY ,  FARABOSCHI, Paolo ,  SUCH-VICENTE, Alberto

IPC: G06F09/38

CPC classification number: G06F12/1441 ,  G06F9/3842 ,  G06F9/3879

Abstract: A computer system includes a CPU for executing conventional instructions and speculative instructions, and a memory controller coupled to a system bus. In response to an access operation by one of the instructions, the CPU generates a speculative instruction bit and a corresponding access address. The access address represents a location in a global address space which includes a first address space and a second address space. The speculative instruction bit is asserted when the corresponding access address is generated by a speculative instruction. The memory controller discards the access operation when the speculative instruction bit is asserted and the access address is in the second address space. Thus, the speculative instruction is prevented from accessing the second address space. In one embodiment, the computer system includes a memory coupled to the system bus and mapped to the first address space, and an I/O device coupled to the system bus and mapped to the second address space. The speculative instruction is prevented from accessing the I/O device.

Abstract translation: 计算机系统包括用于执行常规指令和推测指令的CPU以及耦合到系统总线的存储器控​​制器。 响应于指令之一的访问操作，CPU产生推测指令位和相应的访问地址。 访问地址表示全局地址空间中包含第一地址空间和第二地址空间的位置。 当相应的访问地址由推测指令生成时，推测指令位被置位。 当推测指令位被置位并且访问地址位于第二地址空间时，存储器控制器丢弃访问操作。 因此，防止推测指令访问第二地址空间。 在一个实施例中，计算机系统包括耦合到系统总线并映射到第一地址空间的存储器以及耦合到系统总线并被映射到第二地址空间的I / O设备。 禁止推测指令访问I / O设备。