公开(公告)号：WO1998027485A1

公开(公告)日：1998-06-25

申请号：PCT/US1997022643

申请日：1997-12-12

Applicant: HEWLETT-PACKARD COMPANY

Inventor： HEWLETT-PACKARD COMPANY ,  FARABOSCHI, Paolo ,  SUCH-VICENTE, Alberto

IPC: G06F09/38

CPC classification number: G06F12/1441 ,  G06F9/3842 ,  G06F9/3879

Abstract: A computer system includes a CPU for executing conventional instructions and speculative instructions, and a memory controller coupled to a system bus. In response to an access operation by one of the instructions, the CPU generates a speculative instruction bit and a corresponding access address. The access address represents a location in a global address space which includes a first address space and a second address space. The speculative instruction bit is asserted when the corresponding access address is generated by a speculative instruction. The memory controller discards the access operation when the speculative instruction bit is asserted and the access address is in the second address space. Thus, the speculative instruction is prevented from accessing the second address space. In one embodiment, the computer system includes a memory coupled to the system bus and mapped to the first address space, and an I/O device coupled to the system bus and mapped to the second address space. The speculative instruction is prevented from accessing the I/O device.

Abstract translation: 计算机系统包括用于执行常规指令和推测指令的CPU以及耦合到系统总线的存储器控​​制器。 响应于指令之一的访问操作，CPU产生推测指令位和相应的访问地址。 访问地址表示全局地址空间中包含第一地址空间和第二地址空间的位置。 当相应的访问地址由推测指令生成时，推测指令位被置位。 当推测指令位被置位并且访问地址位于第二地址空间时，存储器控制器丢弃访问操作。 因此，防止推测指令访问第二地址空间。 在一个实施例中，计算机系统包括耦合到系统总线并映射到第一地址空间的存储器以及耦合到系统总线并被映射到第二地址空间的I / O设备。 禁止推测指令访问I / O设备。