公开(公告)号：KR860000159B1

公开(公告)日：1986-02-27

申请号：KR820002234

申请日：1982-05-21

Applicant: HITACHI LTD

Inventor： MINATO OSAMU ,  SASAKI DOSHIO ,  KINOSHITA MASAMI ,  MASUHARA DOSHIAKI ,  SASAKI YUKIO ,  SAKAI YOSHIO

IPC: H01L27/08 ,  G11C5/00 ,  G11C11/412 ,  H01L21/8238 ,  H01L21/8244 ,  H01L27/092 ,  H01L27/11 ,  H01L29/78

Abstract: A semiconductor substrate has on its surface an impurity, well of different conductivity. The impurity well has a second impurity well of the same conductivity as that of the first one therein. The second impurity well has a higher impurity density and a lower depth than the first one. The second impurity well has a third well of the same conductivity as that of the substrate therein. The memory cell array, consisting of field effect transistors, has its source and drain at the impurity wells.

公开(公告)号：DE3271101D1

公开(公告)日：1986-06-19

申请号：DE3271101

申请日：1982-02-25

Applicant: HITACHI LTD

Inventor： YOSHIDA ISAO ,  OKABE TAKEAKI ,  KATSUEDA MINEO ,  NAGATA MINORU ,  MASUHARA TOSHIAKI ,  ASHIKAWA KAZUTOSHI ,  KATO HIDEAKI ,  ITO MITSUO ,  OHTAKA SHIGEO ,  MINATO OSAMU ,  SAKAI YOSHIO

IPC: H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H01L29/78 ,  H01L29/861 ,  H01L23/56

公开(公告)号：DE3036869A1

公开(公告)日：1981-04-16

申请号：DE3036869

申请日：1980-09-30

Applicant: HITACHI LTD

Inventor： MASUHARA TOSHIAKI ,  MINATO OSAMU ,  SHIMOHIGASHI KATSUHIRO ,  MASUDA HIROO ,  SUNAMI HIDEO ,  SAKAI YOSHIO ,  KAMIGAKI YOSHIAKI ,  TAKEDA EIJI ,  HAGIWARA YOSHIMUNE

IPC: G11C8/10 ,  G11C17/16 ,  G11C17/18 ,  G11C29/00 ,  H01L21/263 ,  H01L21/268 ,  H01L21/768 ,  H01L23/525 ,  H01L27/10 ,  G11C5/12 ,  G06F11/20 ,  H01L27/04 ,  H01L21/72 ,  H01L23/56

Abstract: A programmable semiconductor integrated circuitry including a circuit programming element is disclosed. The circuit programming element can be activated in a short-circuit mode by the irradiation of a laser or electron beam or by ion implantation so that it is converted from its original nonconductive state into a conductive or conductable state, thereby providing electrical connection between circuits and/or circuit elements of the integrated circuitry for a desired circuit programming such as circuit creation, circuit conversion or circuit substitution.

公开(公告)号：HK44286A

公开(公告)日：1986-06-27

申请号：HK44286

申请日：1986-06-19

Applicant: HITACHI LTD

Inventor： NAGASAWA KOUICHI ,  SAKAI YOSHIO ,  MINATO OSAMU ,  MASUHARA TOSHIAKI ,  MEGURO SATOSHI

IPC: H01L29/78 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8244 ,  H01L23/485 ,  H01L23/522 ,  H01L23/532 ,  H01L27/11 ,  H01L23/52

公开(公告)号：CA1205571A

公开(公告)日：1986-06-03

申请号：CA445161

申请日：1984-01-12

Applicant: HITACHI LTD

Inventor： KOMORIYA GOH ,  HANAMURA SHOJI ,  AOKI MASAAKI ,  MINATO OSAMU ,  MASUHARA TOSHIAKI

IPC: H01L27/08 ,  H01L21/8238 ,  H01L21/8244 ,  H01L27/092 ,  H01L27/11 ,  H01L29/66 ,  H01L29/78 ,  H01L23/34

Abstract: : A CMOS type semiconductor integrated circuit consisting of p-channel MOS transistors and n-channel MOS transistors, is operated at temperatures lower than 100.degree.K. Power and input signals are applied thereto, and output signals are taken out therefrom. The advantages of high speed operation, high density of integration and low power consumption are obtained.

公开(公告)号：DE2904812A1

公开(公告)日：1979-08-16

申请号：DE2904812

申请日：1979-02-08

Applicant: HITACHI LTD

Inventor： MINATO OSAMU ,  MASUHARA TOSHIAKI ,  SASAKI TOSHIO ,  KUBO MASAHARU

IPC: H01L21/822 ,  G11C11/412 ,  H01L21/8238 ,  H01L27/04 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L29/78 ,  G11C11/40 ,  G11C7/00 ,  H01L27/08

Abstract: The device has a first trough zone (3) produced on the surface of a semiconductor substrate (1) to which a specified voltage is applied. There is a store section (101) which is fitted in the trough zone (3), and a section (100) forming the peripheral circuit outside the first through zone (3). It contains corresponding elements. The transistor system is designed to act as an N-channel MOSFET with a p-conducting trough (2). The first trough zone (3) is p-conducting, it contains at least one p-conducting layer (51).

公开(公告)号：DE2834759A1

公开(公告)日：1979-02-15

申请号：DE2834759

申请日：1978-08-08

Applicant: HITACHI LTD

Inventor： MASUHARA TOSHIAKI ,  MINATO OSAMU ,  SAKAI YOSHIO ,  SASAKI TOSHIO ,  KUBO MASAHARU ,  NISHIMURA KOTARO ,  YASUI TOKUMASA

IPC: H03F1/52 ,  H01L21/02 ,  H01L21/822 ,  H01L23/62 ,  H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H01L27/08 ,  H01L29/78 ,  H03F1/42 ,  H01L23/56

Abstract: On the surface of an insulating film formed on the surface of a semiconductor substrate on which an MOS type semiconductor device to be protected is formed, there are formed a first polycrystal silicon member having input and output terminals and a resistivity lower than 1 K OMEGA / &squ& and a second polycrystalline silicon member having a resistivity lower than 1 K OMEGA / &squ& and being maintained at a fixed potential. This second polycrystalline silicon member faces at least a part of the first silicon member with polycrystalline silicon of a resistivity higher than 100 K OMEGA / &squ& interposed therebetween. The input terminal of the first polycrystalline silicon member is connected to an input pad of the MOS type semiconductor device to be protected and the output terminal of the first polycrystalline silicon member is connected to an input gate of the semiconductor device to be protected. The input gate of the semiconductor device is protected by utilizing the punch-through effect in the interior of the polycrystalline silicon having a resistivity higher than 100 K OMEGA / &squ& .

公开(公告)号：MY8600547A

公开(公告)日：1986-12-31

申请号：MY8600547

申请日：1986-12-30

Applicant: HITACHI LTD ,  HITACHI MICROCUMPUTER ENG

Inventor： YASUI TOKUMASA ,  NAKAMURA HIDEAKI ,  UCHIBORI KIYOFUMI ,  TANIMURA NOBUYOSHI ,  MINATO OSAMU

IPC: G11C11/417 ,  G11C11/409 ,  G11C11/419 ,  H01L27/11 ,  G11C5/02 ,  G11C7/00 ,  H01L27/04

公开(公告)号：CA1200328A

公开(公告)日：1986-02-04

申请号：CA430676

申请日：1983-06-17

Applicant: HITACHI LTD

Inventor： YAMAMOTO SYUICHI ,  HASHIMOTO NORIKAZU ,  SASAKI TOSHIO ,  MASUHARA TOSHIAKI ,  MINATO OSAMU ,  TAMAKI YOICHI ,  HAYASHIDA TETSUYA

IPC: H01L27/08 ,  H01L21/762 ,  H01L27/092 ,  H01L29/78 ,  H01L29/06

Abstract: : A semiconductor device with a well structure is designed to avoid the undesirable phenomenon known as latch-up, attributable to a parasitic element, and to enhance the density of integration. For this purpose a groove-like insulator layer is formed at a boundary between the well region and the semiconductor body to extend in the depthwise direction of the semiconductor body. This insulator layer separates the conductive regions that constitute the parasitic element. As a result, latch-up is avoided, the area of the well region can be made small and the density of integration can be made about 1.4 times higher than in a prior-art LSI.

公开(公告)号：GB2141871A

公开(公告)日：1985-01-03

申请号：GB8403595

申请日：1984-02-10

Applicant: HITACHI LTD

Inventor： NAGASAWA KOUICHI ,  SAKAI YOSHIO ,  MINATO OSAMU ,  MASUHARA TOSHIAKI ,  MEGURO SATOSHI

IPC: H01L29/78 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8244 ,  H01L23/485 ,  H01L23/522 ,  H01L23/532 ,  H01L27/11 ,  H01L27/04