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    MIX MODE SIMULATION SYSTEM
    2.
    发明专利
    MIX MODE SIMULATION SYSTEM 失效

    公开(公告)号：JPH05159017A

    公开(公告)日：1993-06-25

    申请号：JP5421592

    申请日：1992-02-05

    Applicant: HITACHI LTD

    Inventor： SUGIHARA HITOSHI ,  KINOSHITA MASAMI ,  HOJO SABURO ,  YAMASHIRO OSAMU ,  YOKOMIZO KOICHI ,  MIYAMA MIKAKO ,  IWABUCHI MASATO ,  OGAWA MUNEHIRO

    IPC: G06F11/25 ,  G01R31/3167 ,  G06F17/50

    Abstract: PURPOSE:To highly precisely simulate the interlocking characteristic of a circuit while considering the influence of current consumed in a digital circuit part to an analog circuit part by calculating the current of the digital circuit part in an equivalent circuit part for current calculation. CONSTITUTION:The analog circuit part 805 and the equivalent circuit part for current calculation 804 recognized from a digital circuit part 810 are included in a circuit simulation objective circuit 820 being the object of circuit simulation. The equivalent circuit part for the current calculation 804 of the digital circuit part 810 is formed by making current flowing in the digital circuit part 810 into a model. The synthesis circuit of the equivalent circuit part for current calculation 804 and the analog circuit part 805 is circuit-simulated by a circuit simulator by adding the equivalent circuit part for current calculation 804 to the analog circuit part 805.

    MIXED-MODE SIMULATION SYSTEM
    3.
    发明专利
    MIXED-MODE SIMULATION SYSTEM 失效

    公开(公告)号：JPH0512372A

    公开(公告)日：1993-01-22

    申请号：JP18536791

    申请日：1991-06-29

    Applicant: HITACHI LTD

    Inventor： MIYAMA MIKAKO ,  YOKOMIZO KOICHI ,  KINOSHITA MASAMI ,  SUGIHARA HITOSHI ,  HOJO SABURO ,  IWABUCHI MASATO

    IPC: G01R31/28 ,  G06F11/25 ,  G06F11/26 ,  G06F17/50

    Abstract: PURPOSE:To provide the mixed-mode simulation system which shorten the time required for simulation. CONSTITUTION:Analysis switching time tC is determined according to earlier time between next expected time td when a signal is passed from a circuit part which performs logic simulation to a circuit part which performs circuit simulation and next expected time ta when the circuit simulation is performed; and the logic simulation is performed until the analysis switching time tC, then the circuit simulation is performed, and those are repeated to advance the simulation. Consequently, time steps of the circuit simulation need not be made fine and the efficient mixed-mode simulation is performed. Further, no back track is generated, so unnecessary calculation is reducible.

    SEMICONDUCTOR INTEGRATED CIRCUIT
    4.
    发明专利
    SEMICONDUCTOR INTEGRATED CIRCUIT 失效

    公开(公告)号：JPS57192064A

    公开(公告)日：1982-11-26

    申请号：JP7650381

    申请日：1981-05-22

    Applicant: HITACHI LTD

    Inventor： MINATO OSAMU ,  MASUHARA TOSHIAKI ,  SASAKI TOSHIO ,  SASAKI YUKIO ,  KINOSHITA MASAMI ,  SAKAI YOSHIO ,  NAGASAWA KOUICHI

    IPC: H01L27/08 ,  G11C5/00 ,  G11C11/412 ,  H01L21/8238 ,  H01L21/8244 ,  H01L27/092 ,  H01L27/11 ,  H01L29/78

    Abstract: PURPOSE:To form a memory cell having a small occupying area without reducing storage capacity of the memory cell by providing a highly concentrated, P type impurity layer beneath an N type impurity layer which is a storing node. CONSTITUTION:On an N type Si substrate 1, a drain 6, a source 21, and gate 7 of an N channel MOSFET and a drain 21, a source 22, and a gate 24 of an N channel MOS FET are formed. The highly concentrated P type impurity layer 30 is provided beneath the N type impurity layer which is the storing layer 21. As a result, the junction capacity of the storing node 21 is increased about twice, the stored charge is increased, and the potential difference of about 0.2V is generated between a P type well and the highly concentrated, P type impurity layer 30 due to the difference in concentration between them. The electrons, which are generated by the irradiation of alpha particles in the P type well based on said electric field, are stored in the P type well, and do not affect the N type impurity layer which is the upper storing node.

    SIMULATION SYSTEM
    5.
    发明专利
    SIMULATION SYSTEM 失效

    公开(公告)号：JPH04317175A

    公开(公告)日：1992-11-09

    申请号：JP11114991

    申请日：1991-04-16

    Applicant: HITACHI LTD

    Inventor： YAMASHIRO OSAMU ,  KINOSHITA MASAMI ,  SUGIHARA HITOSHI

    IPC: H01L21/66 ,  G01R31/28 ,  G06F17/50 ,  H01L21/82

    Abstract: PURPOSE:To obtain a technique which can highly precisely simulate the interlocking characteristic of an analog circuit and a digital circuit of analog/ digital mixing LSI. CONSTITUTION:A current calculation circuit 4 formed by modelling a current flowing in the digital circuit 1 is added to the analog circuit 5 and the synthesis circuit 20 is analog-simulated. Thus, the fluctuation of a consumption current in the digital circuit 1 can be reflected on the analog circuit 5 on a real time basis and the interlocking characteristic of the analog circuit 5 and the digital circuit 1 can be simulated.

    FORMATION OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    6.
    发明专利
    FORMATION OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效

    公开(公告)号：JPH0290548A

    公开(公告)日：1990-03-30

    申请号：JP24113288

    申请日：1988-09-28

    Applicant: HITACHI LTD ,  HITACHI COMPUTER ENG

    Inventor： NOMOTO KAZUYUKI ,  IWABUCHI MASATO ,  YAMAHA KEIICHI ,  KINOSHITA MASAMI ,  OIDA ATSUSHI

    IPC: H01L21/822 ,  G06F17/50 ,  H01L21/82 ,  H01L27/04

    Abstract: PURPOSE:To reduce lower cells as a commonness between a pre-treatment and a post-treatment is secured by a method wherein a compaction treatment is performed on the patterns, on which the patterns of upper wirings are synthesized, of the lower cells. CONSTITUTION:A position, where a plurality of pieces of lower cells 2 arranged in a semiconductor integrated circuit device (LSI) 1 are used in common, is specified and the positions of these cells 2 are stored. Then, the patterns of upper wirings 3, which intrude within the ranges of the cells 2 and do not belong to the cells 2, are cut out at ranges 2' of the cells 2 and the positions of these ranges 2' are recorded. Then, the patterns, which are cut out at the ranges 2', of the wirings 3 are superposed on the patterns of the cells 2 and a synthetic treatment of the respective patterns is performed. Then, a compaction treatment is performed on the patterns, on which the patterns of the wirings 3 are synthesized, of the cells 2 and the pattern of a lower cell 20 and the pattern of an upper wiring 30 are isolated from each other in every wiring position in the device 1 at a range 20' that the pattern of the upper wiring 30 is cut out from the pattern, on which a compaction treatment is performed and which is synthesized, of the lower cell 20.

    SEMICONDUCTOR MEMORY INTEGRATED CIRCUIT
    7.
    发明专利
    SEMICONDUCTOR MEMORY INTEGRATED CIRCUIT 失效

    公开(公告)号：JPS60137000A

    公开(公告)日：1985-07-20

    申请号：JP25649184

    申请日：1984-12-06

    Applicant: HITACHI LTD

    Inventor： MINATO OSAMU ,  MASUHARA TOSHIAKI ,  SASAKI TOSHIO ,  KINOSHITA MASAMI ,  SASAKI YUKIO

    IPC: G11C11/413 ,  G11C29/00 ,  G11C29/04

    Abstract: PURPOSE:To attain relieve of fault by means of a few program element numbers by arranging a switching circuit between a column decoder and a column selection gate circuit, transmitting an output signal of a decoder for column selection of a defective memory column to a spare column selection gate circuits so as to select a spare cell. CONSTITUTION:When an element 101 is a defective cell, it is replaced with a spare cell 110 by irradiating a laser to a program element 129 so as to bring the resistance to a low value. A high level voltage 132 is transmitted immediately to an element 135 via the element 129, the 135 reaches a high level voltage and the spare cell 110 is selected. In the level of a source terminal 161 connected to a gate of the gate circuit of the defective cell 101, 1 pMOS transistor 126 is nonconductive, an nMOS123 is conductive, the voltage is a low level voltage, the defective cell 101 is not selected and the defective cell is replaced with the spare cell. The number of elements to be programmed is very less and the time required for defect relieve is reduced remarkably.

    SEMICONDUCTOR MEMORY
    8.
    发明专利
    SEMICONDUCTOR MEMORY 失效

    公开(公告)号：JPS60167188A

    公开(公告)日：1985-08-30

    申请号：JP27065284

    申请日：1984-12-24

    Applicant: HITACHI LTD

    Inventor： SASAKI TOSHIO ,  MINATO OSAMU ,  SASAKI YUKIO ,  KINOSHITA MASAMI ,  MASUHARA TOSHIAKI

    IPC: G11C11/41 ,  G11C7/00

    Abstract: PURPOSE:To decrease the current consumption of a data line by dividing the memory and cell and block configuration of a word unit through a logic gate into plural pieces connecting said pieces with a common data line and separately reading out said blocks by selection of an X decoder. CONSTITUTION:Word lines WL.L and WL.R of memory are devided to the right/left through an X decoder for every 16 rows of one-block 32-row memory cells so as to simultaneously input/output eight bits of memory cell MC selection. By taking logic with one address signal, for example, A8 in the X decoder XDEC, either of left word line WL.L or right word line WL.R is activated. As a result, the word lines for memory cell selection is reduced to half, and the current consumption flowing through a data line load MOS transistor LMOS, and the memory cell MC can be reduced to half.

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