公开(公告)号：WO0003507A3

公开(公告)日：2001-06-14

申请号：PCT/US9915365

申请日：1999-07-08

Applicant: HYUNDAI ELECTRONICS AMERICA

Inventor： KANG INCHUL ,  LAUDEL KENNAN

IPC: H03L7/08 ,  H04B1/707 ,  H04B1/7075 ,  H04B1/7077 ,  H04B1/7085 ,  H04B1/709 ,  H04J11/00 ,  H04J13/00 ,  H04B15/00 ,  H04K1/00 ,  H04L27/30

CPC classification number: H04B1/7085 ,  H04B1/70757 ,  H04B1/7077 ,  H04B1/709 ,  H04B2201/70707 ,  H04J13/0022

Abstract: A variable rate correlation circuit (fig.3) for conserving power includes a variable clock source (340), a local PN source (360), and a correlator (320). The local PN source (360) further includes a local generator (361) and a resampler (364). The variable clock source (340) provides a normal clock rate and a lower clock rate. The local generator (361) supplies the local PN sequence at the normal clock rate. The resampler (364) receives the local PN sequence sampled at the normal clock rate and output the local PN sequence sampled at the lower clock rate. The correlator (320) receives the lower sampled local PN sequence, the received PN sequence, and the lower clock rate signal, correlating the received and local PN sequences at the lower clock rate to produce a correlated result.

Abstract translation: 用于节省功率的可变速率相关电路（图3）包括可变时钟源（340），本地PN源（360）和相关器（320）。 本地PN源（360）还包括本地发生器（361）和重采样器（364）。 可变时钟源（340）提供正常的时钟速率和较低的时钟速率。 本地发生器（361）以正常时钟速率提供本地PN序列。 重采样器（364）接收以正常时钟速率采样的本地PN序列，并输出以较低时钟速率采样的本地PN序列。 相关器（320）接收较低采样的本地PN序列，接收的PN序列和较低时钟速率信号，使接收到的本地PN序列以较低的时钟速率相关，以产生相关结果。

公开(公告)号：WO0003493A2

公开(公告)日：2000-01-20

申请号：PCT/US9914625

申请日：1999-06-28

Applicant: HYUNDAI ELECTRONICS AMERICA

Inventor： KANG INCHUL ,  SUN WINSTON Y

IPC: H04B1/7097 ,  H04B1/71 ,  H04B1/7115 ,  H04B7/02 ,  H04B7/00

CPC classification number: H04B1/7097 ,  H04B1/7101 ,  H04B1/7115

Abstract: The present invention provides a CDMA receiver which uses less expensive, more manufacturable digital filters in combination with noise cancellation circuitry to attenuate highly correlated signals. In addition, the CDMA receiver employs digital IF sampling in the baseband conversion process to remove superimposed DC voltages from the baseband data, obviating the need for DC offset voltage generators.

Abstract translation: 本发明提供了一种CDMA接收机，其使用较便宜的，更可制造的数字滤波器与噪声消除电路结合来衰减高度相关的信号。 此外，CDMA接收机在基带转换过程中采用数字中频采样，以从基带数据中去除叠加的直流电压，从而避免了对直流失调电压发生器的需要。

公开(公告)号：DE69924277T2

公开(公告)日：2006-03-30

申请号：DE69924277

申请日：1999-07-08

Applicant: HYUNDAI ELECTRONICS AMERICA SA

Inventor： KANG INCHUL ,  LAUDEL KENNAN

IPC: H03L7/08 ,  H04B15/00 ,  H04B1/707 ,  H04B1/7075 ,  H04B1/7077 ,  H04B1/7085 ,  H04B1/709 ,  H04J11/00 ,  H04J13/00 ,  H04K1/00

Abstract: A variable rate correlation circuit for conserving power includes a variable clock source, a local PN source, and a correlator. The local PN source further includes a local generator and a resampler. The variable clock source provides a normal clock rate and a lower clock rate. The local generator supplies the local PN sequence at the normal clock rate. The resampler receives the local PN sequence sampled at the normal clock rate and outputs the local PN sequence sampled at the lower clock rate. The correlator receives the lower sampled local PN sequence, the received PN sequence, and the lower clock rate signal, correlating the received and local PN sequences at the lower clock rate to produce a. correlated result.

公开(公告)号：DE69924277D1

公开(公告)日：2005-04-21

申请号：DE69924277

申请日：1999-07-08

Applicant: HYUNDAI ELECTRONICS AMERICA SA

Inventor： KANG INCHUL ,  LAUDEL KENNAN

IPC: H03L7/08 ,  H04B1/707 ,  H04B1/7075 ,  H04B1/7077 ,  H04B1/7085 ,  H04B1/709 ,  H04J11/00 ,  H04J13/00 ,  H04B15/00 ,  H04K1/00

Abstract: A variable rate correlation circuit for conserving power includes a variable clock source, a local PN source, and a correlator. The local PN source further includes a local generator and a resampler. The variable clock source provides a normal clock rate and a lower clock rate. The local generator supplies the local PN sequence at the normal clock rate. The resampler receives the local PN sequence sampled at the normal clock rate and outputs the local PN sequence sampled at the lower clock rate. The correlator receives the lower sampled local PN sequence, the received PN sequence, and the lower clock rate signal, correlating the received and local PN sequences at the lower clock rate to produce a. correlated result.

公开(公告)号：AT291299T

公开(公告)日：2005-04-15

申请号：AT99932333

申请日：1999-07-08

Applicant: HYUNDAI ELECTRONICS AMERICA

Inventor： KANG INCHUL ,  LAUDEL KENNAN

IPC: H03L7/08 ,  H04B1/707 ,  H04B1/7075 ,  H04B1/7077 ,  H04B1/7085 ,  H04B1/709 ,  H04J11/00 ,  H04J13/00 ,  H04B15/00 ,  H04K1/00

Abstract: A variable rate correlation circuit for conserving power includes a variable clock source, a local PN source, and a correlator. The local PN source further includes a local generator and a resampler. The variable clock source provides a normal clock rate and a lower clock rate. The local generator supplies the local PN sequence at the normal clock rate. The resampler receives the local PN sequence sampled at the normal clock rate and outputs the local PN sequence sampled at the lower clock rate. The correlator receives the lower sampled local PN sequence, the received PN sequence, and the lower clock rate signal, correlating the received and local PN sequences at the lower clock rate to produce a. correlated result.

公开(公告)号：EP1125383A4

公开(公告)日：2004-04-21

申请号：EP99932333

申请日：1999-07-08

Applicant: HYUNDAI ELECTRONICS AMERICA

Inventor： KANG INCHUL ,  LAUDEL KENNAN

IPC: H03L7/08 ,  H04B1/707 ,  H04B1/7075 ,  H04B1/7077 ,  H04B1/7085 ,  H04B1/709 ,  H04J11/00 ,  H04J13/00 ,  H04B15/00 ,  H04K1/00

CPC classification number: H04B1/7085 ,  H04B1/70757 ,  H04B1/7077 ,  H04B1/709 ,  H04B2201/70707 ,  H04J13/0022

Abstract: A variable rate correlation circuit (fig.3) for conserving power includes a variable clock source (340), a local PN source (360), and a correlator (320). The local PN source (360) further includes a local generator (361) and a resampler (364). The variable clock source (340) provides a normal clock rate and a lower clock rate. The local generator (361) supplies the local PN sequence at the normal clock rate. The resampler (364) receives the local PN sequence sampled at the normal clock rate and output the local PN sequence sampled at the lower clock rate. The correlator (320) receives the lower sampled local PN sequence, the received PN sequence, and the lower clock rate signal, correlating the received and local PN sequences at the lower clock rate to produce a correlated result.

公开(公告)号：EP1097535A4

公开(公告)日：2005-04-06

申请号：EP99933780

申请日：1999-07-08

Applicant: HYUNDAI ELECTRONICS AMERICA

Inventor： KANG INCHUL

IPC: H04B1/28 ,  H04B1/40 ,  H04J1/00

CPC classification number: H04B1/405

Abstract: The present invention provides for an improved transceiver architecture using fewer frequency synthesizers. The number of frequency synthesizers is reduced by utilizing an existing frequency source having a frequency slightly offset from the ideal sampling frequency. In one embodiment, an improved transceiver capable of communicating CDMA encoded signals is presented. The transceiver includes a first frequency synthesizer (260) producing a first mixing tone (261), a second frequency synthesizer (270) producing a second mixing tone (271), a first sampling source (290) producing a first sampling signal, and a receiving channel. The receiving channel includes a first mixer (232), a second mixer (235), and an analog to digital converter (ADC). The first mixer (232) receives the incoming CDMA signal and the first mixing tone, producing a first IF signal. The second mixer (235) receives the first IF signal and second mixing tone, producing a second IF signal in response. The ADC receives the second IF signal and the first samplingsignal, producing a digital data stream in response, whereby the frequency of the first sampling signal is offset from the frequency of the second IF signal, the digital data having a small amount of error associated therewith in proportion to the small amount of the frequency offset.