公开(公告)号：WO9835344A2

公开(公告)日：1998-08-13

申请号：PCT/US9802740

申请日：1998-02-11

Applicant: HYUNDAI ELECTRONICS AMERICA

Inventor： LEE JONG SEUK

IPC: G11C16/04 ,  G11C16/08 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  G11B

CPC classification number: H01L27/11519 ,  G11C16/0416 ,  G11C16/08

Abstract: The present invention provides a novel nonvolatile Flash EEPROM array design which allows for array, block or sector erase capabilities. The relatively simple transistor design layout of the present invention allows small portions of the EEPROM array to be erased without affecting data stored in the remaining portion of the array. In addition, given the block structured layout of the Flash EEPROM array, adjacent blocks in the array can share transistor control circuitry, thus minimizing the size of the array. The novel nonvolatile Flash EEPROM array preferably comprises a plurality of blocks which comprise a plurality of sectors of NOR-gate transistors. Each transistor has a drain, a source, and a control gate. Preferably, the drains of each transistor in a column are electrically coupled, the control gates of each transistor in a row are electrically coupled, and the sources of all the transistors in a sector are electrically coupled. A sector of the nonvolatile Flash EEPROM array preferably comprises 8 rows and 512 columns of transistors and a block preferably comprises 128 vertically stacked sectors.

Abstract translation: 本发明提供了一种新颖的非易失性闪存EEPROM阵列设计，其允许阵列，块或扇区擦除功能。 本发明的相对简单的晶体管设计布局允许擦除EEPROM阵列的小部分而不影响存储在阵列的剩余部分中的数据。 另外，考虑到闪存EEPROM阵列的块结构布局，阵列中的相邻块可以共享晶体管控制电路，从而使阵列的尺寸最小化。 新颖的非易失性闪存EEPROM阵列优选地包括多个块，其包括多个NOR栅极晶体管的扇区。 每个晶体管都有漏极，源极和控制栅极。 优选地，列中每个晶体管的漏极电耦合，一行中的每个晶体管的控制栅极电耦合，并且扇区中的所有晶体管的源电耦合。 非易失性闪存EEPROM阵列的扇区优选地包括8行和512列的晶体管，并且块优选地包括128个垂直堆叠的扇区。

公开(公告)号：DE19880311T1

公开(公告)日：1999-05-12

申请号：DE19880311

申请日：1998-02-11

Applicant: HYUNDAI ELECTRONICS AMERICA

Inventor： LEE JONG SEUK

IPC: G11C16/04 ,  G11C16/08 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  G11C16/02

Abstract: The present invention provides a novel nonvolatile Flash EEPROM array design which allows for array, block or sector erase capabilities. The relatively simple transistor design layout of the present invention allows small portions of the EEPROM array to be erased without affecting data stored in the remaining portion of the array. In addition, given the block structured layout of the Flash EEPROM array, adjacent blocks in the array can share transistor control circuitry, thus minimizing the size of the array. The novel nonvolatile Flash EEPROM array preferably comprises a plurality of blocks which comprise a plurality of sectors of NOR-gate transistors. Each transistor has a drain, a source, and a control gate. Preferably, the drains of each transistor in a column are electrically coupled, the control gates of each transistor in a row are electrically coupled, and the sources of all the transistors in a sector are electrically coupled. A sector of the nonvolatile Flash EEPROM array preferably comprises 8 rows and 512 columns of transistors and a block preferably comprises 128 vertically stacked sectors.

公开(公告)号：DE19880311B3

公开(公告)日：2017-06-22

申请号：DE19880311

申请日：1998-02-11

Applicant: HYUNDAI ELECTRONICS AMERICA INC

Inventor： LEE JONG SEUK

IPC: G11C16/04 ,  G11C16/08 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: Die vorliegende Erfindung schafft einen neuen nichtflüchtigen Flash-EEPROM-Matrixentwurf, der Matrix-, Block- oder Sektor-Löschfähigkeiten ermöglicht. Die relativ einfache Konstruktion des Transistorentwurfs der vorliegenden Erfindung ermöglicht das Löschen kleiner Abschnitte der EEPROM-Matrix ohne Beeinflussung von Daten, die in dem restlichen Abschnitt der Matrix gespeichert sind. Außerdem können angrenzende Blöcke in der Matrix unter der Voraussetzung der Blockstruktur-Konstruktion der Flash-EEPROM-Matrix eine Transistor-Steuerschaltungsanordnung gemeinsam nutzen, was somit die Größe der Matrix minimiert. Die neue nichtflüchtige Flash-EEPROM-Matrix enthält zweckmäßig mehrere Blöcke, die mehrere Sektoren aus NOR-Gatter-Transistoren enthalten. Jeder Transistor besitzt einen Drain, eine Source und ein Steuer-Gate. Zweckmäßig sind die Drains jedes Transistors in einer Spalte elektrisch gekoppelt, sind die Steuer-Gates jedes Transistors in einer Zeile elektrisch gekoppelt und sind die Sources aller Transistoren in einem Sektor elektrisch gekoppelt. Zweckmäßig umfaßt ein Sektor der nichtflüchtigen Flash-EEPROM-Matrix 8 Zeilen und 512 Spalten aus Transistoren, wobei ein Block zweckmäßig 128 vertikal gestapelte Sektoren umfaßt.

公开(公告)号：GB2326748B

公开(公告)日：2001-09-12

申请号：GB9820270

申请日：1998-02-11

Applicant: HYUNDAI ELECTRONICS AMERICA

Inventor： LEE JONG SEUK

IPC: G11C16/04 ,  G11C16/08 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  G11C16/16

Abstract: The present invention provides a novel nonvolatile Flash EEPROM array design which allows for array, block or sector erase capabilities. The relatively simple transistor design layout of the present invention allows small portions of the EEPROM array to be erased without affecting data stored in the remaining portion of the array. In addition, given the block structured layout of the Flash EEPROM array, adjacent blocks in the array can share transistor control circuitry, thus minimizing the size of the array. The novel nonvolatile Flash EEPROM array preferably comprises a plurality of blocks which comprise a plurality of sectors of NOR-gate transistors. Each transistor has a drain, a source, and a control gate. Preferably, the drains of each transistor in a column are electrically coupled, the control gates of each transistor in a row are electrically coupled, and the sources of all the transistors in a sector are electrically coupled. A sector of the nonvolatile Flash EEPROM array preferably comprises 8 rows and 512 columns of transistors and a block preferably comprises 128 vertically stacked sectors.

公开(公告)号：GB2326748A

公开(公告)日：1998-12-30

申请号：GB9820270

申请日：1998-02-11

Applicant: HYUNDAI ELECTRONICS AMERICA

Inventor： LEE JONG SEUK

IPC: G11C16/04 ,  G11C16/08 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  G11C16/06

Abstract: The present invention provides a novel nonvolatile Flash EEPROM array design which allows for array, block or sector erase capabilities. The relatively simple transistor design layout of the present invention allows small portions of the EEPROM array to be erased without affecting data stored in the remaining portion of the array. In addition, given the block structured layout of the Flash EEPROM array, adjacent blocks in the array can share transistor control circuitry, thus minimizing the size of the array. The novel nonvolatile Flash EEPROM array preferably comprises a plurality of blocks which comprise a plurality of sectors of NOR-gate transistors. Each transistor has a drain, a source, and a control gate. Preferably, the drains of each transistor in a column are electrically coupled, the control gates of each transistor in a row are electrically coupled, and the sources of all the transistors in a sector are electrically coupled. A sector of the nonvolatile Flash EEPROM array preferably comprises 8 rows and 512 columns of transistors and a block preferably comprises 128 vertically stacked sectors.