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    HYBRID SYNAPTIC ARCHITECTURE BASED NEURAL NETWORK
    2.
    发明申请
    HYBRID SYNAPTIC ARCHITECTURE BASED NEURAL NETWORK 审中-公开
    基于混合突触结构的神经网络

    公开(公告)号：WO2017074440A1

    公开(公告)日：2017-05-04

    申请号：PCT/US2015/058397

    申请日：2015-10-30

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： MURALIMANOHAR, Naveen ,  STRACHAN, John Paul ,  BALASUBRAMONIAN, Rajeev ,  WILLIAMS, R. Stanley

    IPC: G06N3/063 ,  G06N3/04

    CPC classification number: G06N3/063 ,  G06N3/0635

    Abstract: According to an example, a hybrid synaptic architecture based neural network may be implemented by determining, from input data, information that is to be recognized, mined, and/or synthesized by a plurality of analog neural cores. Further, the hybrid synaptic architecture based neural network may be implemented by determining, based on the information, selected ones of the plurality of analog neural cores that are to be actuated to identify a data subset of the input data to generate, based on the analysis of the data subset, results of the recognition, mining, and/or synthesizing of the information.

    Abstract translation: 根据一个例子，基于混合突触架构的神经网络可以通过从输入数据确定要被识别，挖掘和/或由多个模拟神经核合成的信息来实现 。 此外，基于混合突触架构的神经网络可以通过基于该信息确定要被致动的多个模拟神经核中的选定模拟神经核来基于分析来识别要生成的输入数据的数据子集 的数据子集，识别，挖掘和/或合成信息的结果。

    DRAINING A WRITE QUEUE BASED ON INFORMATION FROM A READ QUEUE
    3.
    发明申请
    DRAINING A WRITE QUEUE BASED ON INFORMATION FROM A READ QUEUE 审中-公开
    根据阅读队列的信息排出一个写作队列

    公开(公告)号：WO2016068986A1

    公开(公告)日：2016-05-06

    申请号：PCT/US2014/063357

    申请日：2014-10-31

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： MURALIMANOHAR, Naveen ,  BALASUBRAMONIAN, Rajeev

    IPC: G06F12/06

    CPC classification number: G06F12/0806 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/084 ,  G06F13/161 ,  G06F13/1642 ,  G06F2212/1024 ,  G06F2212/283 ,  G06F2212/502 ,  G06F2212/621 ,  G11C7/00

    Abstract: A method to access a memory chip having memory banks includes processing read requests in a read queue, and when a write queue is filled beyond a high watermark, stopping the processing of the read requests in the read queue and draining the write queue until the write queue is under a low watermark. Draining the write queue include issuing write requests in an order based on information in the read queue. When the write queue is under the low watermark, the method includes stopping the draining of the write queue and again processing the read requests in the read queue.

    Abstract translation: 访问具有存储体的存储器芯片的方法包括处理读取队列中的读取请求，并且当写入队列被填充超过高水印时，停止读取队列中的读取请求的处理并排出写入队列直到写入 队列处于低水位下。 排出写入队列包括基于读取队列中的信息以顺序发出写入请求。 当写入队列低于低水印时，该方法包括停止写入队列的排出并再次处理读取队列中的读取请求。

    DETERMINING A CURRENT IN A MEMORY ELEMENT OF A CROSSBAR ARRAY
    5.
    发明申请
    DETERMINING A CURRENT IN A MEMORY ELEMENT OF A CROSSBAR ARRAY 审中-公开
    确定十字架阵列的记忆元素中的电流

    公开(公告)号：WO2016122627A1

    公开(公告)日：2016-08-04

    申请号：PCT/US2015/013877

    申请日：2015-01-30

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： MURALIMANOHAR, Naveen ,  BALASUBRAMONIAN, Rajeev ,  FOLTIN, Martin

    IPC: G11C13/00 ,  G11C5/06

    CPC classification number: G11C13/003 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0069 ,  G11C29/50 ,  G11C2013/0054 ,  G11C2013/0057 ,  G11C2029/5006 ,  G11C2213/72 ,  G11C2213/76

    Abstract: A method of determining a current in a memory element of a crossbar array is described. In the method, a number of pre-access operations are initiated. Each pre-access operation includes discarding a previously stored sneak current, determining a new sneak current for the crossbar array, discarding a previously stored sneak current, and storing the new sneak current. In the method, in response to a received access command, an access voltage is applied to a target memory element of the crossbar array and an element current for the target memory element is determined based on an access current and a stored sneak current.

    Abstract translation: 描述了确定交叉开关阵列的存储元件中的电流的方法。 在该方法中，启动了许多预访问操作。 每个预访问操作包括丢弃先前存储的潜行电流，确定交叉开关阵列的新潜行电流，丢弃先前存储的潜行电流并存储新的潜行电流。 在该方法中，响应于接收到的访问命令，将访问电压施加到交叉开关阵列的目标存储器元件，并且基于存取电流和存储的潜行电流来确定目标存储器元件的元件电流。

    DATA BLOCK WRITE MAPPED TO MEMORY BANK
    6.
    发明申请
    DATA BLOCK WRITE MAPPED TO MEMORY BANK 审中-公开
    数据块写入映射到存储器银行

    公开(公告)号：WO2016195704A1

    公开(公告)日：2016-12-08

    申请号：PCT/US2015/034375

    申请日：2015-06-05

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： BALASUBRAMONIAN, Rajeev ,  LESARTRE, Gregg B. ,  SCHREIBER, Robert ,  MURALIMANOHAR, Naveen

    IPC: G06F12/06

    CPC classification number: H04N19/00 ,  G06F12/023 ,  G06F2212/1044 ,  G06F2212/401 ,  G06T9/00

    Abstract: Techniques for data block write mapped to memory bank are provided. In one aspect, a block of data to be written to a line in a bank of a rank of memory may be received. The rank of memory may comprise multiple banks, and the block of data may be written to a number of memory devices determined by the size of the data block. A memory device mapping may be retrieved. The mapping may determine the order in which the block of data is written to the memory devices within the rank. It may be determined when the banks of the memory devices used to store the line are available for writing. The block of data may be written to the banks of the memory devices when the banks are available for writing.

    Abstract translation: 提供了映射到存储体的数据块写入技术。 在一个方面，可以接收要写入存储器等级的存储体中的行的数据块。 存储器的等级可以包括多个存储体，并且数据块可以写入由数据块的大小确定的多个存储器件。 可以检索存储器设备映射。 映射可以确定将数据块写入等级内的存储器件的顺序。 用于存储线路的存储器件的存储体可用于写入。 当银行可用于写入时，数据块可以被写入存储器件的存储体。

    COMPRESSED DATA BLOCK MAPPING
    7.
    发明申请
    COMPRESSED DATA BLOCK MAPPING 审中-公开
    压缩数据块映射

    公开(公告)号：WO2016195702A1

    公开(公告)日：2016-12-08

    申请号：PCT/US2015/034368

    申请日：2015-06-05

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： BALASUBRAMONIAN, Rajeev ,  LESARTRE, Gregg B. ,  SCHREIBER, Robert ,  MURALIMANOHAR, Naveen

    IPC: G06F12/06

    CPC classification number: G06F12/023 ,  G06F2212/1044 ,  G06F2212/401 ,  G06T9/00 ,  H04N19/00

    Abstract: Techniques for compressed data block mapping are provided. In one aspect, a request to retrieve a block of data stored in memory devices in a rank of memory may be received. The mapping that was used when the data block was stored may be determined. The retrieved data block may be ordered based on the determined mapping. The block of data may be decompressed.

    Abstract translation: 提供了压缩数据块映射技术。 在一个方面，可以接收到检索存储在存储器等级的存储器件中的数据块的请求。 可以确定在存储数据块时使用的映射。 所检索的数据块可以基于所确定的映射来排序。 数据块可以被解压缩。

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