公开(公告)号：DE19512431A1

公开(公告)日：1995-11-02

申请号：DE19512431

申请日：1995-04-03

Applicant: IBM

Inventor： ACOVIC ALEXANDRE ,  WU BEN SONG

IPC: H01L21/8247 ,  H01L21/84 ,  H01L27/105 ,  H01L27/115 ,  H01L27/12 ,  H01L29/786 ,  H01L29/788 ,  H01L29/792

Abstract: A stacked gate memory cell for a memory cell array is disclosed that is constructed on a SOI substrate and contains a second control gate buried underneath the conducting channel of the cell in addition to a first wordline control gate that is disposed over a floating gate changing the voltage on the second control gate will modulate the potential of the floating channel, which allows a specific cell of the array to be selected and the programmed or erased by FN tunneling through the floating gate and channel without disturbing adjacent cells. While reading the information stored in the floating gate, the second control gate can also be used to prevent disturb. The second control gate is in parallel with the bit line and perpendicular with the first word line control gate. The floating gate and the cell is located at the cross point of the first and second control gates. Therefore, by varying the voltage on the first and second control gates only, the cell can be programmed or erased through FN tunneling.

公开(公告)号：DE19511846A1

公开(公告)日：1995-11-02

申请号：DE19511846

申请日：1995-03-31

Applicant: IBM

Inventor： ACOVIC ALEXANDRE ,  WU BEN SONG

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L27/12 ,  H01L29/788 ,  H01L29/792

公开(公告)号：DE19512431C2

公开(公告)日：2001-09-13

申请号：DE19512431

申请日：1995-04-03

Applicant: IBM

Inventor： ACOVIC ALEXANDRE ,  WU BEN SONG

IPC: H01L21/8247 ,  H01L21/84 ,  H01L27/105 ,  H01L27/115 ,  H01L27/12 ,  H01L29/786 ,  H01L29/788 ,  H01L29/792

Abstract: A stacked gate memory cell for a memory cell array is disclosed that is constructed on a SOI substrate and contains a second control gate buried underneath the conducting channel of the cell in addition to a first wordline control gate that is disposed over a floating gate changing the voltage on the second control gate will modulate the potential of the floating channel, which allows a specific cell of the array to be selected and the programmed or erased by FN tunneling through the floating gate and channel without disturbing adjacent cells. While reading the information stored in the floating gate, the second control gate can also be used to prevent disturb. The second control gate is in parallel with the bit line and perpendicular with the first word line control gate. The floating gate and the cell is located at the cross point of the first and second control gates. Therefore, by varying the voltage on the first and second control gates only, the cell can be programmed or erased through FN tunneling.

公开(公告)号：IE79078B1

公开(公告)日：1998-04-08

申请号：IE970456

申请日：1997-06-17

Applicant: IBM

Inventor： ACOVIC ALEXANDRE ,  NING TAK HUNG ,  SOLOMON PAUL MICHAEL

IPC: H01L21/8247 ,  H01L27/115 ,  H01L27/12 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

Abstract: An electrically erasable programmable read-only memory CEEPROM) includes a field effect transistor and a control gate spaced apart on a first insulating layer, a second insulating layer formed over the field effect transistor and the control gate and a common floating gate on the second insulating layer over the channel of the field effect transistor and the control gate, the floating gate thus also forms the gate electrode of the field-effect transistor. The EEPROM devices may be interconnected in a memory array and a plurality of memory arrays may be stacked on upon another. The invention overcomes the problem of using a non-standard silicon-on-insulator (SOI) CMOS process to make EEPROM arrays with high areal density.

公开(公告)号：IE970456A1

公开(公告)日：1998-01-28

申请号：IE970456

申请日：1997-06-17

Applicant: IBM

Inventor： ACOVIC ALEXANDRE ,  NING TAK HUNG ,  SOLOMON PAUL MICHAEL

IPC: H01L21/8247 ,  H01L27/115 ,  H01L27/12 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

Abstract: An EEPROM device is described incorporating a field effect transistor and a control gate spaced apart on a first insulating layer, a second insulating layer formed over the field effect transistor and the control gate and a common floating gate on the second insulating layer over the channel of the field effect transistor and the control gate, the floating gate thus also forms the gate electrode of the field-effect transistor. The EEPROM devices may be interconnected in a memory array and a plurality of memory arrays may be stacked on upon another. The invention overcomes the problem of using a non-standard silicon-on-insulator (SOI) CMOS process to make EEPROM arrays with high areal density.

公开(公告)号：DE19511846C2

公开(公告)日：1997-09-18

申请号：DE19511846

申请日：1995-03-31

Applicant: IBM

Inventor： ACOVIC ALEXANDRE ,  WU BEN SONG

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L27/12 ,  H01L29/788 ,  H01L29/792