公开(公告)号：WO03021672A3

公开(公告)日：2003-07-24

申请号：PCT/GB0203837

申请日：2002-08-19

Applicant: IBM ,  IBM UK

Inventor： ALCOE DAVID ,  LI LI ,  SATHE SANJEEV BALWANT

IPC: H01L23/00 ,  H01L23/373 ,  H05K1/02 ,  H05K1/11 ,  H05K3/46 ,  H01L23/498

CPC classification number: H01L23/562 ,  H01L23/3735 ,  H01L2224/16 ,  H01L2924/01025 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K1/0203 ,  H05K1/0271 ,  H05K1/112 ,  H05K3/4602 ,  H05K2201/09781 ,  H05K2201/10674 ,  H05K2201/2009

Abstract: An electronic package and method of making same in which a circuitized substrate having a first stiffness includes a plurality of electrically conductive circuit members on a first portion of the circuitized substrate and is adapted for having solder connections thereon and for being electrically connected to a semiconductor chip. A stiffener layer having a second stiffness is positioned on a second portion of the circuitized substrate relative to the first portion, the second stiffness of the stiffener layer distributing a portion of the first stiffness of said circuitized substrate so as to substantially prevent failure of the solder connections between the electrically conductive circuit members and the semiconductor chip during operation of the electronic package.

Abstract translation: 一种电子封装及其制造方法，其中具有第一刚度的电路化衬底包括在电路化衬底的第一部分上的多个导电电路构件，并且适于在其上具有焊接连接并且用于电连接到半导体芯片 。 具有第二刚度的加强层相对于第一部分位于电路化基板的第二部分上，加强层的第二刚度分布所述电路化基板的第一刚度的一部分，以便基本上防止焊料的故障 在电子封装的操作期间导电电路部件与半导体芯片之间的连接。

公开(公告)号：AU2002329376A1

公开(公告)日：2003-03-18

申请号：AU2002329376

申请日：2002-08-19

Applicant: IBM

Inventor： ALCOE DAVID ,  SATHE SANJEEV BALWANT ,  LI LI

IPC: H01L23/00 ,  H01L23/373 ,  H05K1/02 ,  H05K1/11 ,  H05K3/46 ,  H01L23/498

Abstract: An electronic package and method of making same in which a circuitized substrate having a first stiffness includes a plurality of electrically conductive circuit members on a first portion of the circuitized substrate and is adapted for having solder connections thereon and for being electrically connected to a semiconductor chip. A stiffener layer having a second stiffness is positioned on a second portion of the circuitized substrate relative to the first portion, the second stiffness of the stiffener layer distributing a portion of the first stiffness of said circuitized substrate so as to substantially prevent failure of the solder connections between the electrically conductive circuit members and the semiconductor chip during operation of the electronic package.