公开(公告)号：MY109414A

公开(公告)日：1997-01-31

申请号：MYPI19922119

申请日：1992-11-20

Applicant: IBM

Inventor： ALFREDO ALDEREGUIA ,  NADER AMINI ,  RICHARD LOUIS HORNE ,  CHANG NGOC TRAN ,  TERENCE JOSEPH LOHMAN

IPC: G06F13/14 ,  G06F13/16 ,  G06F13/36

Abstract: A COMPUTER SYSTEM IS PROVIDED, COMPRISING SYSTEM MEMORY AND A MEMORY CONTROLLER FOR CONTROLLING ACCESS TO SYSTEM MEMORY, A CENTRAL PROCESSING UNIT ELECTRICALLY CONNECTED WITH THE MEMORY CONTROLLER, AND A BUS INTERFACE UNIT ELECTRICALLY CONNECTED TO THE MEMORY CONTROLLER BY A SYSTEM BUS AND ELECTRICALLY CONNECTED TO AN INPUT/OUTPUT DEVICE BY AN INPUT/OUTPUT BUS. THE BUS INTERFACE UNIT INCLUDES TRANSLATION LOGIC FOR TEMPORARILY STORING, IN RESPONSE TO A PREDETERMINED SET OF OPERATING CONDITIONS, DATA TRANSFERRED BETWEEN THE SYSTEM THE SYSTEM BUS AND THE INPUT/OUTPUT BUS THROUGH THE BUS INTERFACE UNIT. THE PREDETERMINED SET OF OPERATING CONDITIONS OCCUR WHEN (I) THE MEMORY CONTROLLER ON BEHALF OF THE CENTRAL PROCESSING UNIT WRITES DATA TO THE INPUT/OUTPUT DEVICE, OR (II) THE MEMORY CONTROLLER ON BEHALF OF THE CENTRAL PROCESSING UNIT INITIATES A READ OR WRITE CYCLE DESTINED FOR THE INPUT/OUTPUT DEVICE ACTING AS A SLAVE ON THE INPUT/OUTPUT BUS, AND THE DATA BUS WIDTH OF THE MEMORY CONTROLLER IS GREATER THAN A CORRESPONDING DATA BUS WIDTH OF THE INPUT/OUTPUT DEVICE.

公开(公告)号：HK1000067A1

公开(公告)日：1997-11-07

申请号：HK97101599

申请日：1997-07-23

Applicant: IBM

Inventor： ALFREDO ALDEREGUIA ,  CARVIS CROMER DARYL ,  MAURICE BLAND PATRICK ,  MAX STUTES ROGER

IPC: G11C11/401 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/42 ,  G11C11/407 ,  G06F

Abstract: A data processing system includes a memory controller for accessing a dynamic memory having a plurality of SIMMs that differ in size and speed of operation. The memory controller is operable in response to a request to access a given SIMM to read a SIMM definition register and dynamically produce memory access signals in accordance with the timing requirements of the particular SIMM being accessed. Such signals are set each time a SIMM is accessed. The signals provide different clock periods of RAS precharge time, RAS to CAS time, and CAS pulse width.