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    BIDIRECTIONAL DATA STORAGE FACILITY FOR BUS INTERFACE UNIT
    1.
    发明专利
    BIDIRECTIONAL DATA STORAGE FACILITY FOR BUS INTERFACE UNIT 未知

    公开(公告)号：MY114231A

    公开(公告)日：2002-09-30

    申请号：MYPI19922125

    申请日：1992-11-20

    Applicant: IBM

    Inventor： BECHARA FOUAD BOURY ,  NADER AMINI ,  SHERWOOD BRANNON ,  RICHARD LOUIS HORNE ,  TERENCE JOSEPH LOHMAN

    IPC: G06F13/16 ,  G06F13/40 ,  G06F13/28

    Abstract: A METHOD AND SYSTEM ARE PROVIDED FOR CONTROLLING DATA TRANSFER BETWEEN A SYSTEM MEMORY (24,26) CONNECTED TO A SYSTEM BUS (76) AND AT LEAST ONE INPUT/OUTPUT (I/O) DEVICE (28) CONNECTED TO AN I/O BUS (32) IN A COMPUTER SYSTEM (10). THE SYSTEM BUS IS COUPLED TO THE I/O BUS BY A BUS INTERFACE UNIT (64) COMPRISING A FIRST PAIR OF BUFFERS (125A, 125C) CONNECTED IN SERIES BETWEEN THE I/O BUS AND THE SYSTEM BUS, AND A SECOND PAIL OF BUFFERS (125B, 125D) CONNECTED IN SERIES BETWEEN THE I/O BUS AND THE SYSTEM BUS AND IN PARALLEL WITH THE FIRST PAIR OF BUFFERS. EACH OF THE BUFFERS IN EACH OF THE PAIRS IS USED FOR BIDIRECTIONAL DATA TRANSFER BETWEEN THE SYSTEM BUS AND THE I/O BUS. FIG.1

    BUS INTERFACE LOGIC FOR COMPUTER SYSTEM HAVING DUAL BUS ARCHITECTURE
    2.
    发明专利
    BUS INTERFACE LOGIC FOR COMPUTER SYSTEM HAVING DUAL BUS ARCHITECTURE 未知

    公开(公告)号：MY109414A

    公开(公告)日：1997-01-31

    申请号：MYPI19922119

    申请日：1992-11-20

    Applicant: IBM

    Inventor： ALFREDO ALDEREGUIA ,  NADER AMINI ,  RICHARD LOUIS HORNE ,  CHANG NGOC TRAN ,  TERENCE JOSEPH LOHMAN

    IPC: G06F13/14 ,  G06F13/16 ,  G06F13/36

    Abstract: A COMPUTER SYSTEM IS PROVIDED, COMPRISING SYSTEM MEMORY AND A MEMORY CONTROLLER FOR CONTROLLING ACCESS TO SYSTEM MEMORY, A CENTRAL PROCESSING UNIT ELECTRICALLY CONNECTED WITH THE MEMORY CONTROLLER, AND A BUS INTERFACE UNIT ELECTRICALLY CONNECTED TO THE MEMORY CONTROLLER BY A SYSTEM BUS AND ELECTRICALLY CONNECTED TO AN INPUT/OUTPUT DEVICE BY AN INPUT/OUTPUT BUS. THE BUS INTERFACE UNIT INCLUDES TRANSLATION LOGIC FOR TEMPORARILY STORING, IN RESPONSE TO A PREDETERMINED SET OF OPERATING CONDITIONS, DATA TRANSFERRED BETWEEN THE SYSTEM THE SYSTEM BUS AND THE INPUT/OUTPUT BUS THROUGH THE BUS INTERFACE UNIT. THE PREDETERMINED SET OF OPERATING CONDITIONS OCCUR WHEN (I) THE MEMORY CONTROLLER ON BEHALF OF THE CENTRAL PROCESSING UNIT WRITES DATA TO THE INPUT/OUTPUT DEVICE, OR (II) THE MEMORY CONTROLLER ON BEHALF OF THE CENTRAL PROCESSING UNIT INITIATES A READ OR WRITE CYCLE DESTINED FOR THE INPUT/OUTPUT DEVICE ACTING AS A SLAVE ON THE INPUT/OUTPUT BUS, AND THE DATA BUS WIDTH OF THE MEMORY CONTROLLER IS GREATER THAN A CORRESPONDING DATA BUS WIDTH OF THE INPUT/OUTPUT DEVICE.

    ARBITRATION CONTROL LOGIC FOR COMPUTER SYSTEM HAVING DUAL BUS ARCHITECTURE
    3.
    发明专利
    ARBITRATION CONTROL LOGIC FOR COMPUTER SYSTEM HAVING DUAL BUS ARCHITECTURE 未知

    公开(公告)号：MY112381A

    公开(公告)日：2001-06-30

    申请号：MYPI19922116

    申请日：1992-11-20

    Applicant: IBM

    Inventor： NADER AMINI ,  RICHARD LOUIS HORNE ,  BECHARA FOUAD BOURY ,  TERENCE JOSEPH LOHMAN

    IPC: G06F13/00 ,  D06F35/00

    Abstract: A COMPUTER. SYSTEM(10) IS PROVIDED COMPRISING SYSTEM MEMORY(24) AND A MEMORY CONTROLLER( 58) FOR CONTROLLING ACCESS TO SYSTEM MEMORY, A CENTRAL PROCESSING UNIT(38) ELECTRICALLY CONNECTED WITH THE MEMORY CONTROLLER, AND A BUS INTERFACE UNIT(64) ELECTRICALLY CONNECTED TO THE MEMORY CONTROLLER BY A SYSTEM BUS(76) AND ELECTRICALLY CONNECTED TO A PLURALITY OF INPUT/OUTPUT DEVICES(28) BY AN INPUT/OUTPUT BUS(32) .THE BUS INTERFACE UNIT IS ABLE TO SENSE WHEN SAID ONE OF SAID INPUT/OUTPUT DEVICES HAS COMPLETED A READ OR WRITE OPERATION OVER SAID INPUT/OUTPUT BUS, AND INCLUDES A BUFFER CIRCUIT(74) WHEREIN READ AND WRITE DATA TRANSFERRED BETWEEN THE SYSTEM BUS AND THE INPUT/OUTPUT BUS VIA THE BUS INTERFACE UNIT IS TEMPORARILY STORED DURING THE TRANSFER. ARBITRATION CONTROL LOGIC RESIDES IN SAID BUS INTERFACE UNIT AND INTERACTS WITH A CENTRAL ARBITRATION CONTROLLER( 62) WHICH RESIDES ON THE SYSTEM BUS. THE CENTRAL ARBITRATION CONTROLLER RESPONDS TO THE ARBITRATION CONTROL LOGIC TO SIMULTANEOUSLY PERFORM (I) ARBITRATION CYCLES WHEREIN THE CENTRAL ARBITRATION CONTROLLER ARBITRATES BETWEEN THE PLURALITY OF INPUT/OUTPUT DEVICES AND THE CENTRAL PROCESSING UNIT TO DETERMINE WHICH OF THE INPUT/OUTPUT DEVICES OR THE CENTRAL PROCESSING UNIT SHOULD BE GRANTED CONTROL OF THE INPUT/OUTPUT BUS AND (II) GRANT CYCLES WHEREIN THE CENTRAL ARBITRATION CONTROLLER GRANTS CONTROL OF THE INPUT/OUTPUT BUS AND EXTENDS CONTROL OF THE SYSTEM BUS TO ONE OF THE INPUT/OUTPUT DEVICES OR (FIG. 1)

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