公开(公告)号：DE1774896B1

公开(公告)日：1972-05-31

申请号：DE1774896

申请日：1968-09-27

Applicant: IBM

Inventor： ALLEN BELL KENNETH ,  JOSEPH KLATZ RAYMOND ,  ROCHESTER MINN ,  EARL WALLIS DONALD ,  KAY WOMACK KARL

IPC: G06F3/00 ,  G06F9/34 ,  G06F12/04 ,  G06F13/10 ,  G06F13/34 ,  G06F15/78 ,  G06F13/00 ,  G06F9/00

Abstract: 1,233,951. Data processing. INTERNATIONAL BUSINESS MACHINES CORP. 23 Aug., 1968 [27 Sept., 1967], No. 40417/68. Heading G4A. A data processing system comprises a main store for data and control words, an auxiliary store capable of performing a plurality of read/ write cycles during each read/write cycle of the main store, means to read out a multi-byte word from the main store and selective transfer means to transfer a multi-byte data word to the auxiliary store or a multi-byte control word to a control register, means to send a data word in the auxiliary store a byte at a time to an arithmetic logic unit for processing and to store the result in the auxiliary store, a control word being read from the main store to a control register and decoded to provide a sequence of control signals to control the processing of one byte from at least one data word by the arithmetic logic unit. The main store also stores instruction words. The auxiliary ("active") store has predetermined locations for the instruction counter, main store addresses of two operands, working areas and general purpose registers. Each operand address from the auxiliary store has a word portion for addressing the main store to obtain a (4-byte) operand word which is then stored in one of the auxiliary store working areas. The operand address also has a 2-bit byte portion indicating the first byte of the operand word which actually belongs to this operand. The byte portion is stored in a marker register in a sub-unit accessing and modifier circuit. The marker register has space for two such byte portions (for two operands respectively), and a 4-bit mask which is set as successive bytes are processed to indicate which bytes of the appropriate one of the main store operand words are to be replaced by the processing result when this is transferred into the main store from the auxiliary store. As successive bytes are processed the byte address portions in the marker register are incremented or decremented (according as bytes are taken going rightwards or leftwards along the operand words) by two 2-bit parallel adders which also function as decoders and serve to select, from operand words read from the auxiliary store, successive bytes to be fed to the arithmetic logic unit, and serve to update the mask in the marker register. Control words, besides feeding the control register, the contents of which are decoded to control system operation, also go direct to further decoding circuits, some of which control the main store to read or write a byte, half-word or word, selectively, the information read or written going to or coming from the auxiliary store. Control words also control addressing of the auxiliary store.