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公开(公告)号：DE1774896B1
公开(公告)日：1972-05-31
申请号：DE1774896
申请日：1968-09-27
Applicant: IBM
Inventor： ALLEN BELL KENNETH , JOSEPH KLATZ RAYMOND , ROCHESTER MINN , EARL WALLIS DONALD , KAY WOMACK KARL
Abstract: 1,233,951. Data processing. INTERNATIONAL BUSINESS MACHINES CORP. 23 Aug., 1968 [27 Sept., 1967], No. 40417/68. Heading G4A. A data processing system comprises a main store for data and control words, an auxiliary store capable of performing a plurality of read/ write cycles during each read/write cycle of the main store, means to read out a multi-byte word from the main store and selective transfer means to transfer a multi-byte data word to the auxiliary store or a multi-byte control word to a control register, means to send a data word in the auxiliary store a byte at a time to an arithmetic logic unit for processing and to store the result in the auxiliary store, a control word being read from the main store to a control register and decoded to provide a sequence of control signals to control the processing of one byte from at least one data word by the arithmetic logic unit. The main store also stores instruction words. The auxiliary ("active") store has predetermined locations for the instruction counter, main store addresses of two operands, working areas and general purpose registers. Each operand address from the auxiliary store has a word portion for addressing the main store to obtain a (4-byte) operand word which is then stored in one of the auxiliary store working areas. The operand address also has a 2-bit byte portion indicating the first byte of the operand word which actually belongs to this operand. The byte portion is stored in a marker register in a sub-unit accessing and modifier circuit. The marker register has space for two such byte portions (for two operands respectively), and a 4-bit mask which is set as successive bytes are processed to indicate which bytes of the appropriate one of the main store operand words are to be replaced by the processing result when this is transferred into the main store from the auxiliary store. As successive bytes are processed the byte address portions in the marker register are incremented or decremented (according as bytes are taken going rightwards or leftwards along the operand words) by two 2-bit parallel adders which also function as decoders and serve to select, from operand words read from the auxiliary store, successive bytes to be fed to the arithmetic logic unit, and serve to update the mask in the marker register. Control words, besides feeding the control register, the contents of which are decoded to control system operation, also go direct to further decoding circuits, some of which control the main store to read or write a byte, half-word or word, selectively, the information read or written going to or coming from the auxiliary store. Control words also control addressing of the auxiliary store.
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公开(公告)号：DE1774864B1
公开(公告)日：1972-08-31
申请号：DE1774864
申请日：1968-09-23
Applicant: IBM
Inventor： KAY WOMACK KARL
Abstract: 1,235,927. Data processing. INTERNATIONAL BUSINESS MACHINES CORP. 15 Aug., 1968 [27 Sept., 1967], No. 39074/68. Heading G4A. In a data processing system, words can be transferred a word at a time from a main store holding data and control words to an auxiliary store which is addressable by a plurality of address registers and data from which can be processed a byte at a time. Control words from a main store also holding data and instruction words can be read out to a control register to control, inter alia, read-out in turn of operand address words from predetermined locations of an auxiliary (" active ") store to a memory address register for the main store. The word portion of such an address in the address register addresses the main store to obtain an operand which is inserted into a respective predetermined location in the auxiliary store. The byte portion (two bits) of the address in the address register is inserted in a register in a sub-unit accessing and modifier circuit, this latter register having space for two such byte portions (for two operands respectively) and for a four-bit mask to identify which bytes of one of the operand words in main store are to be finally overwritten with the result of the processing. The mask is preset under control of the appropriate one of the byte address portions. Two adders which also function as decoders are used to increment/decrement the byte portions stored in the register and update the mask as processing (which is serial by byte) proceeds and are used to select, in accordance with the byte address portions, the successive bytes to be supplied to the arithmetic and logic unit from operand word(s) read from the auxiliary store. Addressing of the auxiliary store is under control of section and word select registers the former of which can be controlled from the control register mentioned and both of which can be controlled from a main data bus. However initially the control register addresses the auxiliary store directly via logic. The auxiliary store includes a number of general purpose word registers and the contents of one may be transferred to another via the arithmetic and logic unit a byte at a time under control of four control words (one per byte).
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公开(公告)号：DE1774895A1
公开(公告)日：1972-01-05
申请号：DE1774895
申请日：1968-09-27
Applicant: IBM
Inventor： PORTER HANF WILLIAM , KAY WOMACK KARL
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