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公开(公告)号：US3705393A
公开(公告)日：1972-12-05
申请号：US3705393D
申请日：1970-06-30
Applicant: IBM
Inventor： ANACKER WILHELM , ZAPPE HANS H
CPC classification number: H01L39/223 , G11C11/44 , Y10S505/832
Abstract: A superconducting memory array where the memory cells are superconducting rings, each of which has at least one element therein capable of supporting Josephson tunneling current. Coincident currents are used to trap flux in the rings, and to release the trapped flux for readout of the memory cells. Fast operation and tolerable limits on drive currents are possible if one flux quantum operation is used. To achieve single flux quantum operation, the capacitance, inductance, and damping of each memory cell must be within certain limits.
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公开(公告)号：US3646550A
公开(公告)日：1972-02-29
申请号：US3646550D
申请日：1969-12-24
Applicant: IBM
Inventor： ANACKER WILHELM
CPC classification number: H03M7/00
Abstract: A decoding network with two- or three-dimensional selection capability is composed of magnetic switch elements such as toroidal cores, toroidal films or other films operated in the parallel-field switching mode. Each switch element has a response-excitation characteristic that enables the element to remain in a normal stable state unless it is subjected to an excitation in excess of a given threshold level, whereupon it switches to a different state, at least for the duration of the applied excitation. A coincidence of excitations applied in several selection coordinates may be required to condition an entire set or column of such elements for switching. The elements in each conditioned set or column are selectively switched in response to binary or other bivalued input signals applied to input lines which are individual to the respective elements of any one set but shared by corresponding elements of other sets, the selection of these input signal values constituting still another dimension or coordinate of selection. The input lines are paired so that one selected line of each pair is energized by an input signal of a given binary value. Thus, half of the elements in a set are switched for any given combination of input values. Furthermore, the number of elements switched is always even. A plurality of output lines is associated with each set of elements in such fashion that a unique output line is energized for each different combination of input signal values, with all of the switched elements in the set additively contributing portions of the output signal on that line; whereas in all of the other output lines of that set, the component signals contributed by the switched elements cancel each other out. If toroidal switch elements are used, they are arranged in relatively shiftable planes to facilitate threading the output lines through the switch elements in the desired individual wiring configurations.
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公开(公告)号：US3643237A
公开(公告)日：1972-02-15
申请号：US3643237D
申请日：1969-12-30
Applicant: IBM
Inventor： ANACKER WILHELM
CPC classification number: H03K3/38 , G11C8/00 , G11C11/44 , H01L27/00 , H01L39/223 , Y10S505/832
Abstract: Switching and memory circuits which employ tunneling devices having nonlinearities are made more reliable by making each device a series arrangement of tunnel junctions. This built-in redundancy of each switching element eliminates problems due to frequent device short circuits, especially where there are thin tunnel barriers and the devices are operated under extreme temperature ranges. In a particular case, Josephson devices are used, each of which is a thin film structure having stacked junctions, i.e., a plurality of alternate layers of metal and tunnel barrier.
Abstract translation: 通过使每个器件具有隧道结的串联布置，使得采用具有非线性的隧穿装置的开关和存储电路变得更可靠。 每个开关元件的这种内置冗余消除了由于频繁的器件短路引起的问题，特别是在存在薄的隧道屏障并且器件在极端温度范围内工作的情况下。 在特定情况下，使用约瑟夫逊装置，每个装置是具有层叠结的薄膜结构，即金属和隧道屏障的多个交替层。
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公开(公告)号：US3535694A
公开(公告)日：1970-10-20
申请号：US3535694D
申请日：1968-01-15
Applicant: IBM
Inventor： ANACKER WILHELM , WANG CHU PING
CPC classification number: G06F17/16
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Patent Agency Ranking6.发明授权
公开(公告)号：US3626391A
公开(公告)日：1971-12-07
申请号：US3626391D
申请日：1968-07-15
Applicant: IBM
Inventor： ANACKER WILHELM
IPC: G11C11/44 , H01L39/22 , H03K19/195 , H03K3/38
CPC classification number: H01L39/223 , G11C11/44 , H03K19/1952 , Y10S505/832
Abstract: A memory array comprising memory cells having tunneling gates exhibiting Josephson current. Each memory cell is composed of two Josephson devices, each of which is located in a separate leg of the cell. Drive decoders using Josephson devices are also provided for selection of current into drive, bit, and sense lines (also having Josephson devices) associated with the memory cells. The direction of current flow in a memory cell determines its binary state.
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公开(公告)号：US3466638A
公开(公告)日：1969-09-09
申请号：US3466638D
申请日：1965-12-28
Applicant: IBM
Inventor： ANACKER WILHELM
CPC classification number: G11C11/06042
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公开(公告)号：US3434116A
公开(公告)日：1969-03-18
申请号：US3434116D
申请日：1966-06-15
Applicant: IBM
Inventor： ANACKER WILHELM
CPC classification number: G11C29/76 , G11C11/06007 , G11C29/846 , G11C29/86
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公开(公告)号：GB1287370A
公开(公告)日：1972-08-31
申请号：GB5685870
申请日：1970-11-30
Applicant: IBM
Inventor： ANACKER WILHELM
Abstract: 1287370 Magnetic storage arrangements INTERNATIONAL BUSINESS MACHINES CORP 30 Nov 1970 [24 Dec 1969] 56858/70 Heading H3B [Also in Division G4] A decoder comprises a plurality of pairs of magnetic switching elements, input signals switching one of each pair, a plurality of output means each receiving a signal from each element which switches, the latter signals failing to substantially cancel each other on only one of the output means for each combination of input signals. In Fig. la, toroidal magnetic cores 112-115 are biased to one end of their hysteresis loops by a bias current source (or restore pulses may replace the continuous bias). Two input bits, at 106, 107 respectively, each switch one (depending on the bit value) of cores to the other end of its hysteresis loop, using drive windings 108-111. Output windings each thread every core in one sense or the other depending on the input combination the winding is to recognize. Each pair of drivers, such as 100 -101, may be replaced by one, with one drive winding threading the cores in opposite senses and going to ground (or going to another output of the driver), or the single driver (for the pair of cores) may have two drive windings threading respective cores and going to ground. A preliminary decoder is given in block diagram (logic) form to convert a 2-bit input into signals on 8 leads to drive a decoder having 4 pairs of cores. This 4-pairs decoder may be expanded to have 4 sets of 4 pairs of cores each, the 8 leads above being X leads common to all the sets, and each set having a respective further drive winding (Y lead) threading all its cores, one of the further drive windings being energized, thus (with the 8 leads) providing coincident current selection. This two-dimensional array may be one plane of a three-dimensional array. The function of the bias winding may be taken over by these further drive windings. The cores may be replaced by magnetic film spots, or toroidal films. Coincident current selection may alternatively be done by wiring the Y leads according to the same scheme (in the Y direction) as the X leads are wired (in the X direction). The decoder can be used for energizing half-select lines in a magnetic memory.
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公开(公告)号：CA985792A
公开(公告)日：1976-03-16
申请号：CA170774
申请日：1973-05-04
Applicant: IBM
Inventor： ANACKER WILHELM , MATISOO JURI
IPC: H01L27/18 , H01L39/22 , H03K3/38 , H03K17/92 , H03K19/195
Abstract: Superconductive circuitry using a first Josephson tunneling device connected to a transmission line having a termination such that no reflections result when the Josephson tunneling diode switches between two stable voltage states, in accordance with applied input signals. Means are provided for producing the input signals to switch the first Josephson tunneling device and further Josephson tunneling devices are provided whose voltage state depends on the current pulse delivered to the transmission line when the first Josephson tunneling device switches from a first voltage state to a second voltage state. Logic circuitry is shown using this structure, as well as fan-in and fan-out Josephson tunneling device circuits.
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