公开(公告)号：GB2457147B

公开(公告)日：2012-05-02

申请号：GB0900800

申请日：2009-01-19

Applicant: IBM

Inventor： HESS THOMAS ,  CAUTILLO GIOVANNI ,  WEISS ULRICH ,  ANDRES MICHAEL

IPC: G06F11/14

公开(公告)号：GB2457147A

公开(公告)日：2009-08-12

申请号：GB0900800

申请日：2009-01-19

Applicant: IBM

Inventor： HESS THOMAS ,  CAUTILLO GIOVANNI ,  WEISS ULRICH ,  ANDRES MICHAEL

IPC: G06F11/14

Abstract: Data is written by a master device to a slave device using an I2C bus and then read back to verify that there were no transmission errors. The data may be transferred from a command register 21 on the master into one or more staging registers 23 on the slave, read back from the staging registers and verified by the master. If the data is successfully verified, the master may send a commit command 24 to cause the slave to transfer the data to the corresponding device register 22. After the data is processed, the master may send a copy back command 25 to copy the data back to the staging register. The master may then read the data once more and verify that it is still valid.