公开(公告)号：US3911558A

公开(公告)日：1975-10-14

申请号：US49053174

申请日：1974-07-22

Applicant: IBM

Inventor： ASHAR KANU ,  MAGDO STEVEN

IPC: H01L27/00 ,  H01L29/735 ,  B01J17/00

CPC classification number: H01L27/00 ,  H01L29/735

Abstract: A space charge limited transistor formed on a high resistivity substrate of at least 10,000 ohm-centimeter silicon and of one conductivity type. One surface of the substrate is provided with an impurity zone of the other conductivity type. Spaced diffusions of said one conductivity type are made reaching through the impurity zone to the substrate. The distance separating the spaced diffused areas and the depths of the impurity and of the spaced diffused areas are determined so that a region of high resistivity substrate remains beneath the impurity zone between the spaced diffusions. The dielectric relaxation time within said region is much larger than the carrier transit time whereby space charge limited current flow is achieved upon the establishment of suitable bias conditions.

Abstract translation: 形成在至少10,000欧姆厘米硅和一种导电类型的高电阻率基底上的空间电荷限制晶体管。 衬底的一个表面设置有另一导电类型的杂质区。 使所述一种导电类型的间隔扩散通过杂质区到达衬底。 确定隔开的扩散区域和杂质深度以及间隔扩散区域的距离，使得高电阻率衬底的区域保留在间隔扩散之间的杂质区域的下方。 所述区域内的电介质弛豫时间远远大于载体传播时间，由此在建立合适的偏压条件时实现空间电荷限制电流流动。

公开(公告)号：DE2256447A1

公开(公告)日：1973-06-20

申请号：DE2256447

申请日：1972-11-17

Applicant: IBM

Inventor： ASHAR KANU

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/74 ,  H01L21/761 ,  H01L27/00 ,  H01L19/00

Abstract: An improved self-isolated semiconductor integrated circuit structure is formed by a novel process beginning with diffusing a plurality of N-type buried layers onto a P-type substrate and epitaxially growing a thin P-type layer over the surface of the P-type substrate. Base regions are formed by diffusing a plurality of P-type regions into the P-type epitaxial layer. Collector contact regions and emitter regions are formed by simultaneously diffusing a plurality of N-type regions into the P-type epitaxial layer, the collector contact regions being spaced from the P-type base region and diffused through the epitaxial layer to contact the N-type buried layer, and the emitter regions being diffused within the P-type base regions. A semiconductor integrated circuit structure results having base regions with controllable wide range concentration levels, formed with only three selective diffusion process steps.

公开(公告)号：CA993569A

公开(公告)日：1976-07-20

申请号：CA159059

申请日：1972-12-13

Applicant: IBM

Inventor： ASHAR KANU

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/74 ,  H01L21/761 ,  H01L27/00

Abstract: An improved self-isolated semiconductor integrated circuit structure is formed by a novel process beginning with diffusing a plurality of N-type buried layers onto a P-type substrate and epitaxially growing a thin P-type layer over the surface of the P-type substrate. Base regions are formed by diffusing a plurality of P-type regions into the P-type epitaxial layer. Collector contact regions and emitter regions are formed by simultaneously diffusing a plurality of N-type regions into the P-type epitaxial layer, the collector contact regions being spaced from the P-type base region and diffused through the epitaxial layer to contact the N-type buried layer, and the emitter regions being diffused within the P-type base regions. A semiconductor integrated circuit structure results having base regions with controllable wide range concentration levels, formed with only three selective diffusion process steps.

公开(公告)号：DE2259256A1

公开(公告)日：1973-06-28

申请号：DE2259256

申请日：1972-12-04

Applicant: IBM

Inventor： ASHAR KANU ,  MAGDO STEVEN

IPC: H01L29/80 ,  H01L21/331 ,  H01L21/337 ,  H01L27/00 ,  H01L29/73 ,  H01L29/735 ,  H01L29/78 ,  H01L29/808 ,  H01L11/00

Abstract: 1337906 Semi-conductor devices INTERNATIONAL BUSINESS MACHINES CORP 1 Nov 1972 [17 Dec 1971] 50285/72 Heading H1K A lateral bipolar transistor constituted by N + type emitter and collector regions 4, 5 and P type base region 13 shares the first-mentioned two regions with a space-charge limited transistor whose base region comprises an N- type substrate 1 adjoining the bipolar base region 13. The arrangement is such that, with increasing emitter-base forward bias, a space-charge limited current flows through the space-charge limited transistor under the control of the bipolar base region 13 before the bias reaches a sufficient level to initiate bipolar transistor action through the base region 13. The relatively high gain of the space-charge limited transistor is thus employed at low emitterbase forward biases, and the onset of bipolar action may be retarded further by entirely surrounding the N + type collector region 5 with the N- type material of the substrate 1. The electronic processes involved in the operation of the device are discussed in the Specification. A complementary structure comprising a PNP lateral bipolar transistor in parallel with and sharing the same emitter and collector regions as a PN-P space-charge limited transistor may be integrated into the same semi-conductor substrate 1 as the device shown in Fig. 1 with the addition of no further diffusion steps. The Fig. 1 device is isolated from the complementary device by an N + type guard ring. The conductivity types of the arrangement may be reversed.

公开(公告)号：CA978280A

公开(公告)日：1975-11-18

申请号：CA159072

申请日：1972-12-13

Applicant: IBM

Inventor： ASHAR KANU ,  MAGDO STEVEN

IPC: H01L29/80 ,  H01L21/331 ,  H01L21/337 ,  H01L27/00 ,  H01L29/73 ,  H01L29/735 ,  H01L29/78 ,  H01L29/808

Abstract: 1337906 Semi-conductor devices INTERNATIONAL BUSINESS MACHINES CORP 1 Nov 1972 [17 Dec 1971] 50285/72 Heading H1K A lateral bipolar transistor constituted by N + type emitter and collector regions 4, 5 and P type base region 13 shares the first-mentioned two regions with a space-charge limited transistor whose base region comprises an N- type substrate 1 adjoining the bipolar base region 13. The arrangement is such that, with increasing emitter-base forward bias, a space-charge limited current flows through the space-charge limited transistor under the control of the bipolar base region 13 before the bias reaches a sufficient level to initiate bipolar transistor action through the base region 13. The relatively high gain of the space-charge limited transistor is thus employed at low emitterbase forward biases, and the onset of bipolar action may be retarded further by entirely surrounding the N + type collector region 5 with the N- type material of the substrate 1. The electronic processes involved in the operation of the device are discussed in the Specification. A complementary structure comprising a PNP lateral bipolar transistor in parallel with and sharing the same emitter and collector regions as a PN-P space-charge limited transistor may be integrated into the same semi-conductor substrate 1 as the device shown in Fig. 1 with the addition of no further diffusion steps. The Fig. 1 device is isolated from the complementary device by an N + type guard ring. The conductivity types of the arrangement may be reversed.

公开(公告)号：AU4870672A

公开(公告)日：1974-05-09

申请号：AU4870672

申请日：1972-11-09

Applicant: IBM

Inventor： ASHAR KANU ,  MAGDO STEVEN

IPC: H01L29/80 ,  H01L21/331 ,  H01L21/337 ,  H01L27/00 ,  H01L29/73 ,  H01L29/735 ,  H01L29/78 ,  H01L29/808

Abstract: 1337906 Semi-conductor devices INTERNATIONAL BUSINESS MACHINES CORP 1 Nov 1972 [17 Dec 1971] 50285/72 Heading H1K A lateral bipolar transistor constituted by N + type emitter and collector regions 4, 5 and P type base region 13 shares the first-mentioned two regions with a space-charge limited transistor whose base region comprises an N- type substrate 1 adjoining the bipolar base region 13. The arrangement is such that, with increasing emitter-base forward bias, a space-charge limited current flows through the space-charge limited transistor under the control of the bipolar base region 13 before the bias reaches a sufficient level to initiate bipolar transistor action through the base region 13. The relatively high gain of the space-charge limited transistor is thus employed at low emitterbase forward biases, and the onset of bipolar action may be retarded further by entirely surrounding the N + type collector region 5 with the N- type material of the substrate 1. The electronic processes involved in the operation of the device are discussed in the Specification. A complementary structure comprising a PNP lateral bipolar transistor in parallel with and sharing the same emitter and collector regions as a PN-P space-charge limited transistor may be integrated into the same semi-conductor substrate 1 as the device shown in Fig. 1 with the addition of no further diffusion steps. The Fig. 1 device is isolated from the complementary device by an N + type guard ring. The conductivity types of the arrangement may be reversed.