公开(公告)号：GB2499187A

公开(公告)日：2013-08-14

申请号：GB201201594

申请日：2012-01-31

Applicant: IBM

Inventor： ANSALONI DANILO ,  AUERNHAMMER FLORIAN ALEXANDER ,  DOERING ANDREAS ,  SAGMEISTER PATRICIA MARIA

IPC: G06F12/12 ,  G06F9/44 ,  G06F12/121

Abstract: A cache memory contains cached copies of objects. The objects are checked to see if they contain references to other objects in the cache. The references are checked to see if there are any objects in the cache, which are not referenced by any other objects in the cache. The objects which are not referenced are then evicted from the cache. Type information may be used to identify the references in the objects. The references may be converted to physical memory addresses to identify the objects referenced. Only objects within a specific memory address range may be checked. The address range may be associated with application data and may be assigned to a particular process. Objects in main memory or in a different level cache may be checked.

公开(公告)号：GB2522653A

公开(公告)日：2015-08-05

申请号：GB201401669

申请日：2014-01-31

Applicant: IBM

Inventor： AUERNHAMMER FLORIAN ALEXANDER ,  MCDONALD JOSEPH GERALD

IPC: G06F13/40

Abstract: A bridge for coupling a requesting interconnect and a serving interconnect connected to a number of coherent units in a computer system is disclosed. The bridge includes N machines 131-13N, a tracking entity 121, a first arbiter 122, and a second arbiter 123. Each of the N machines is configured to handle requests from the requesting interconnect and to handle allocated responses from the serving interconnect. Each of the N machines has an allocated local count. The tracking entity is configured to track priorities of the N machines for issuing received requests to the serving interconnect and for issuing received responses to the requesting interconnect based on the N local counts. The first arbiter is configured to arbitrate the received requests to be issued to the serving interconnect based on the tracked priorities. Further, the second arbiter is configured to arbitrate the received responses to he issued to the requesting interconnect based on the tracked priorities. The tracking entity is configured to track the priorities of the N machines for handling requests based on the N local counts and a status of each of the N machines. The invention is said to improve the ordering for requests while supporting retries.

公开(公告)号：DE102016222127A1

公开(公告)日：2017-05-18

申请号：DE102016222127

申请日：2016-11-10

Applicant: IBM

Inventor： AUERNHAMMER FLORIAN ALEXANDER ,  ARNDT RICHARD LOUIS

IPC: G06F9/48

Abstract: Eine Technik zum Verarbeiten von Interrupts in einem Datenverarbeitungssystem beinhaltet ein Empfangen einer Ereignisbenachrichtigungsnachricht (Event Notification Message, ENM) in einer Interruptdarstellungs-Steuereinheit (Interrupt Presentation Controller, IPC). Die ENM gibt eine Ereigniszielnummer, eine Anzahl zu ignorierender Bits, eine Ereignisquellennummer und eine Ereignispriorität an. Die IPC ermittelt eine Gruppe virtueller Prozessor-Threads, die möglicherweise auf der Grundlage der Ereigniszielnummer und der in der ENM angegebenen Anzahl zu ignorierender Bits unterbrochen werden können. Die Ereigniszielnummer kennzeichnet einen bestimmten virtuellen Prozessor-Thread, und die Anzahl zu ignorierender Bits kennzeichnet die Anzahl von Bits niedrigerer Ordnung, die in Bezug auf den betreffenden virtuellen Prozessor-Thread zu ignorieren sind, wenn eine Gruppe virtueller Prozessor-Threads ermittelt wird, die möglicherweise unterbrochen werden können.

公开(公告)号：DE102016222132A1

公开(公告)日：2017-05-18

申请号：DE102016222132

申请日：2016-11-10

Applicant: IBM

Inventor： ARNDT RICHARD LOUIS ,  AUERNHAMMER FLORIAN ALEXANDER

IPC: G06F9/48

Abstract: Eine Technik zum Verarbeiten von Interrupts in einem Datenverarbeitungssystem beinhaltet Empfangen einer Ereignisbenachrichtigungsnachricht (Event Notification Message, ENM) in einer Interrupt-Darstellungs-Steuereinheit (Interrupt Presentation Controller, IPC). Die ENM gibt eine Ebene, eine Ereigniszielnummer und eine Anzahl zu ignorierender Bits an. Die IPC ermittelt eine Gruppe virtueller Prozessor-Threads, die möglicherweise auf der Grundlage der Ereigniszielnummer, der Anzahl zu ignorierender Bits und einer Prozesskennung (ID) unterbrochen werden können, wenn die in der ENM angegebene Ebene einer Benutzerebene entspricht. Die Ereigniszielnummer kennzeichnet einen bestimmten virtuellen Prozessor-Thread, und die Anzahl zu ignorierender Bits kennzeichnet die Anzahl von Bits niedrigerer Ordnung, die in Bezug auf den betreffenden virtuellen Prozessor-Thread zu ignorieren sind, wenn eine Gruppe virtueller Prozessor-Threads ermittelt wird, die möglicherweise unterbrochen werden können.

公开(公告)号：GB2525577A

公开(公告)日：2015-11-04

申请号：GB201401670

申请日：2014-01-31

Applicant: IBM

Inventor： AUERNHAMMER FLORIAN ALEXANDER ,  MCDONALD JOSEPH GERALD

IPC: G06F13/40

Abstract: A bridge 100 for coupling a requesting interconnect and a serving interconnect connected to a number of coherent units in a computer system is proposed. The bridge includes a first interface 111 and an issuer 120. The first interface is configured to receive a read request and a number of write requests that the read request depends on from the requesting interconnect. The issuer is configured to issue the received number of dependent write requests to the serving interconnect. The issuer also issues the received read request to the serving interconnect after issuing the number of dependent write requests and before receiving write acknowledgments for the issued dependent write requests from the serving interconnect. The bridge may further comprise a plurality of read machines 131-13N for handling read requests received at the first interface and a plurality of write machines 141-14M for handling write requests received at the first interface. The read and write machine can be controlled by the issuer. The first interface can be coupled to the requesting interconnect and a second interface can be connected to a serving interconnect, the interfaces each having a plurality of buffers 111-114, 151-154. The invention reduces latency and improves throughput.