公开(公告)号：WO03075154A2

公开(公告)日：2003-09-12

申请号：PCT/EP0302923

申请日：2003-02-27

Applicant: IBM ,  IBM FRANCE ,  DOERING ANDREAS

Inventor： DOERING ANDREAS

IPC: G06F12/08 ,  G06F9/38 ,  G06F9/48

CPC classification number: G06F9/3802 ,  G06F9/383 ,  G06F9/3851

Abstract: Method of prefetching data /instructions related to externally triggered events in a system including an infrastructure (18) having an input interface (20) for receiving data/ instructions to be handled by the infrastructure and an output interface (22) for transmitting data after they have been handled, a memory (14) for storing data/instructions when they are received by input interface, a processor (10) for processing at least some data/instructions, the processor having a cache wherein the data/instructions are stored before being processed, and an external source (26) for assigning sequential tasks to the processor. The method comprises the following steps which are performed while the processor is performing a previous task: determining the location in the memory of data/ instructions to be processed by the processor, indicating to the cache the addresses of these memory locations, fetching the contents of the memory locations and writing them into the cache, and assigning the task of processing the data/instructions to the processor.

Abstract translation: 在包括具有用于接收由基础设施处理的数据/指令的输入接口（20）的基础设施（18）中预取与外部触发的事件有关的数据/指令的方法，以及用于在基础设施之后传送数据的输出接口（22） 处理器（10），用于处理至少一些数据/指令，所述处理器具有高速缓存，其中数据/指令在被存储之前被存储 以及用于将顺序任务分配给处理器的外部源（26）。 该方法包括在处理器执行先前任务时执行的以下步骤：确定存储器中由处理器处理的数据/指令的位置，向高速缓存指示这些存储器位置的地址，取出 存储器位置并将其写入高速缓存，并将处理数据/指令的任务分配给处理器。

公开(公告)号：JP2004206692A

公开(公告)日：2004-07-22

申请号：JP2003393063

申请日：2003-11-21

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DOERING ANDREAS ,  GABRANI MARIA

IPC: G06F9/48 ,  G06F9/46

CPC classification number: G06F9/4831

Abstract: PROBLEM TO BE SOLVED: To provide a method and a device for determining priority values about threads for execution on a multithread processor system.
SOLUTION: The priority values depending on priority-based rating and application priority rating are determined. The priority-based rating represents priority rating of a thread to other threads. The application priority rating represents the priority rating of the threads viewed from an application of the thread.
COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：GB2518631A

公开(公告)日：2015-04-01

申请号：GB201317080

申请日：2013-09-26

Applicant: IBM

Inventor： DOERING ANDREAS ,  DZIEDATAJS RIHARDS

IPC: G05F1/565 ,  G06F1/26

Abstract: A power converter is connectable to a computer device 20 that requires a stable input voltage v1 by a coupling circuitry 30 and comprises a voltage regulator 11 controlling an actual output voltage v2 based on an output reference voltage v3. The output reference voltage v3 is determined and equals a sum of the stable input voltage v1 and the product of the resistance R30 of the coupling circuit 30 and the current I1 measured at the output of the voltage regulator. Coupling circuit 30 can comprise serial wires and connectors and be the sole connection between the converter and the computer device. The output reference voltage v3 can be determined using a temperature compensated resistance of the coupling circuit that can be based on an ambient temperature measurement (fig 4, 17) and a stored temperature compensation model. There can be plural groups of computer devices each group having a regulator for which the output reference voltage v3 is determined as the sum of the input voltage v1 for the group and the product of coupling circuit resistance and measured current of the group. The stable input voltage,v1, the resistance R30 and the temperature compensation model may be stored in a memory that is queried to calculate the reverence voltage.

公开(公告)号：AU2003221510A8

公开(公告)日：2003-09-16

申请号：AU2003221510

申请日：2003-02-27

Applicant: IBM

Inventor： DOERING ANDREAS

IPC: G06F12/08 ,  G06F9/38 ,  G06F9/48

Abstract: Method of prefetching data /instructions related to externally triggered events in a system including an infrastructure (18) having an input interface (20) for receiving data/ instructions to be handled by the infrastructure and an output interface (22) for transmitting data after they have been handled, a memory (14) for storing data/instructions when they are received by input interface, a processor (10) for processing at least some data/instructions, the processor having a cache wherein the data/instructions are stored before being processed, and an external source (26) for assigning sequential tasks to the processor. The method comprises the following steps which are performed while the processor is performing a previous task: determining the location in the memory of data/ instructions to be processed by the processor, indicating to the cache the addresses of these memory locations, fetching the contents of the memory locations and writing them into the cache, and assigning the task of processing the data/instructions to the processor.

公开(公告)号：AU2003221510A1

公开(公告)日：2003-09-16

申请号：AU2003221510

申请日：2003-02-27

Applicant: IBM

Inventor： DOERING ANDREAS

IPC: G06F12/08 ,  G06F9/38 ,  G06F9/48

Abstract: Method of prefetching data /instructions related to externally triggered events in a system including an infrastructure (18) having an input interface (20) for receiving data/ instructions to be handled by the infrastructure and an output interface (22) for transmitting data after they have been handled, a memory (14) for storing data/instructions when they are received by input interface, a processor (10) for processing at least some data/instructions, the processor having a cache wherein the data/instructions are stored before being processed, and an external source (26) for assigning sequential tasks to the processor. The method comprises the following steps which are performed while the processor is performing a previous task: determining the location in the memory of data/ instructions to be processed by the processor, indicating to the cache the addresses of these memory locations, fetching the contents of the memory locations and writing them into the cache, and assigning the task of processing the data/instructions to the processor.

公开(公告)号：CA2478007A1

公开(公告)日：2003-09-12

申请号：CA2478007

申请日：2003-02-27

Applicant: IBM

Inventor： DOERING ANDREAS

IPC: G06F12/08 ,  G06F9/38 ,  G06F9/48

Abstract: Method of prefetching data /instructions related to externally triggered events in a system including an infrastructure (18) having an input interface (20) for receiving data/ instructions to be handled by the infrastructure and an output interface (22) for transmitting data after they have been handled, a memory (14) for storing data/instructions when they are received by input interface, a processor (10) for processing at least some data/instructions, the processor having a cache wherein the data/instructions are stored before being processed, and an external source (26) for assigning sequential tasks to the processor. The method comprises the following steps which are performed while the processor is performing a previous task: determining the location in the memory of data/ instructions to be processed by the processor, indicating to the cache the addresses of these memory locations, fetching the contents of the memory locations and writing them into the cache, and assigning the task of processing the data/instructions to the processor.

公开(公告)号：GB2512378A

公开(公告)日：2014-10-01

申请号：GB201305730

申请日：2013-03-28

Applicant: IBM

Inventor： DOERING ANDREAS ,  LUIJTEN RONALD PETER ,  MICHEL BRUNO ,  PAREDES STEPHEN

IPC: G06F1/18 ,  G06F1/20 ,  H01R12/70

Abstract: A computer module for cooling electronic components of a printed circuit board (PCB) module and for supplying power to those components is suggested. The computer module 200 comprises a PCB module 101 with electronic components 102 attached, and a cooling module 103 connected thereto, the cooling module being arranged in parallel to the printed circuit board and having a first layer 202 which is both thermally and electrically conductive. The first layer is arranged such that heat can be dissipated from the printed circuit board module and power from a power source can be supplied to the electronic components. This allows improved dissipation of heat along with a power supply. The cooling module may include additional layers 203 to provide further heat dissipation and a ground connection, and the cooling module may be connected 303 to a heat sink 301, 302 to remove the dissipated heat. A modular computer system is disclosed which comprises a plurality of these modules.

公开(公告)号：GB2499187A

公开(公告)日：2013-08-14

申请号：GB201201594

申请日：2012-01-31

Applicant: IBM

Inventor： ANSALONI DANILO ,  AUERNHAMMER FLORIAN ALEXANDER ,  DOERING ANDREAS ,  SAGMEISTER PATRICIA MARIA

IPC: G06F12/12 ,  G06F9/44 ,  G06F12/121

Abstract: A cache memory contains cached copies of objects. The objects are checked to see if they contain references to other objects in the cache. The references are checked to see if there are any objects in the cache, which are not referenced by any other objects in the cache. The objects which are not referenced are then evicted from the cache. Type information may be used to identify the references in the objects. The references may be converted to physical memory addresses to identify the objects referenced. Only objects within a specific memory address range may be checked. The address range may be associated with application data and may be assigned to a particular process. Objects in main memory or in a different level cache may be checked.

公开(公告)号：BR0308268A

公开(公告)日：2005-01-04

申请号：BR0308268

申请日：2003-02-27

Applicant: IBM

Inventor： DOERING ANDREAS

IPC: G06F12/08 ,  G06F9/38 ,  G06F9/48

Abstract: Method of prefetching data /instructions related to externally triggered events in a system including an infrastructure (18) having an input interface (20) for receiving data/ instructions to be handled by the infrastructure and an output interface (22) for transmitting data after they have been handled, a memory (14) for storing data/instructions when they are received by input interface, a processor (10) for processing at least some data/instructions, the processor having a cache wherein the data/instructions are stored before being processed, and an external source (26) for assigning sequential tasks to the processor. The method comprises the following steps which are performed while the processor is performing a previous task: determining the location in the memory of data/ instructions to be processed by the processor, indicating to the cache the addresses of these memory locations, fetching the contents of the memory locations and writing them into the cache, and assigning the task of processing the data/instructions to the processor.