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1.发明授权Monolithic memory system with bi-level powering for reduced power consumption 失效具有双电源功能的单片存储器系统，用于降低功耗
公开(公告)号：US3764833A
公开(公告)日：1973-10-09
申请号：US3764833D
申请日：1972-05-22
Applicant: IBM
IPC: G11C11/411 , G11C11/415 , H03K1/02
CPC classification number: G11C11/4116 , G11C11/415
Abstract: An intermittently powered true-complement generator circuit which comprises means for intermittently applying power to said circuit and generator means for receiving a single binary signal bit input prior to the application of said power and for providing a two terminal true-complement output representative of said input only when said power is applied, said generator means providing an output in the up binary state on each of the two output terminals during periods after said signal bit is received and before power is applied.
Abstract translation: 一种间断供电的真实补码发生器电路，其包括用于向所述电路间歇地施加电力的装置和用于在施加所述功率之前接收单个二进制信号位输入的发生器装置，并且用于提供表示所述输入的两端真实补码输出 只有当所述功率被施加时，所述发生器装置在接收到所述信号位之后的周期期间和在施加电力之前在两个输出端子中的每一个上提供处于上二进制状态的输出。
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