公开(公告)号：US3796497A

公开(公告)日：1974-03-12

申请号：US3796497D

申请日：1971-12-01

Applicant: IBM

Inventor： MATHISEN E ,  MOORE R ,  SHEINER L

IPC: G01B11/00 ,  G02B7/00 ,  G03F9/00 ,  H01L21/027 ,  H01L21/30 ,  G01B11/26

CPC classification number: G03F9/70 ,  Y10S438/975

Abstract: An electro-optical mask and wafer alignment system employs alignment patterns on the mask and wafer whose images can be selectively passed through a spatial filter. Each pattern comprises at least two nonparallel lines. The alignment pattern configuration permits the X, Y coordinate locations of at least two corresponding points on the mask and wafer to be sensed by scanning the filtered images of the alignment patterns past a sensing device in a single direction. The mask and/or wafer are then positioned such that the signals generated from the alignment patterns indicate that the corresponding points on the mask and wafer are aligned.

Abstract translation: 电光掩模和晶片对准系统使用掩模和晶片上的对准图案，其图像可以选择性地通过空间滤光器。 每个图案包括至少两个不平行的线。 对准图案配置允许通过沿着单个方向扫描经过感测装置的对准图案的经滤波的图像来感测掩模和晶片上的至少两个对应点的X，Y坐标位置。 然后将掩模和/或晶片定位成使得从对准图案产生的信号指示掩模和晶片上的对应点对齐。

公开(公告)号：US3736573A

公开(公告)日：1973-05-29

申请号：US3736573D

申请日：1971-11-11

Applicant: IBM

Inventor： BLOUNT F ,  GELLER H ,  MOORE R ,  LEUNG H ,  LEWIS S ,  REDMOND J

IPC: G11C11/41 ,  G11C11/411 ,  G11C11/414 ,  G11C11/415 ,  G11C11/416 ,  H03K3/288 ,  H03K17/62 ,  G11C11/40

CPC classification number: G11C11/4116 ,  G11C11/415 ,  G11C11/416 ,  H03K3/288 ,  H03K17/6221

Abstract: A data storage circuit utilizing a bistable memory cell and a resistor sensing bit switch preamplifier for performing read and write operations. The cell contains two double-emitter semiconductor elements having their bases and collectors crosscoupled to form a bistable circuit. Each element has one emitter connected in common to a resistor terminated word line to permit bilevel conduction of the elements from a low level standby state to a higher level power-up state for access operations. The second emitter of each element is coupled through collectoremitter paths of a pair of amplifying and switching transistors to corresponding ones of resistor terminated bit sense lines. The amplifying transistors are concurrently biased on and off by a gating transistor under selective control of a bit driver decoding circuit. In read operations, the stored data is sensed at the bit sense line resistors by a final sense amplifier. For write operations, a write driver is provided to provide appropriate voltages at the bit sense line resistor as required for storage of required data in the memory cell. The final sense amplifier is adapted to be isolated from the circuit by connection to the bit lines through the collector-emitter path of a normally forward-biased control transistor which is reversebiased during write operations.

Abstract translation: 利用双稳态存储单元的数据存储电路和用于执行读和写操作的电阻感测位开关前置放大器。 该电池包含两个双发射极半导体元件，其具有交叉耦合的基极和集电极以形成双稳态电路。 每个元件具有一个共同连接到电阻器端接字线的发射极，以允许元件从低电平待机状态的双电平传导到用于存取操作的较高电平上电状态。 每个元件的第二发射极通过一对放大和开关晶体管的集电极 - 发射极路径耦合到对应的电阻端接的位感测线。 在位驱动器解码电路的选择性控制下，放大晶体管同时被门控晶体管偏置。 在读取操作中，存储的数据通过最终读出放大器在位感测线电阻器处被感测。

公开(公告)号：US3764833A

公开(公告)日：1973-10-09

申请号：US3764833D

申请日：1972-05-22

Applicant: IBM

Inventor： AYLING J ,  MOORE R

IPC: G11C11/411 ,  G11C11/415 ,  H03K1/02

CPC classification number: G11C11/4116 ,  G11C11/415

Abstract: An intermittently powered true-complement generator circuit which comprises means for intermittently applying power to said circuit and generator means for receiving a single binary signal bit input prior to the application of said power and for providing a two terminal true-complement output representative of said input only when said power is applied, said generator means providing an output in the up binary state on each of the two output terminals during periods after said signal bit is received and before power is applied.

Abstract translation: 一种间断供电的真实补码发生器电路，其包括用于向所述电路间歇地施加电力的装置和用于在施加所述功率之前接收单个二进制信号位输入的发生器装置，并且用于提供表示所述输入的两端真实补码输出 只有当所述功率被施加时，所述发生器装置在接收到所述信号位之后的周期期间和在施加电力之前在两个输出端子中的每一个上提供处于上二进制状态的输出。

公开(公告)号：BR7504006A

公开(公告)日：1976-07-06

申请号：BR7505151

申请日：1975-06-26

Applicant: IBM

Inventor： DAVIS D ,  WEBER E ,  WOODARD O ,  HABEGGER M ,  MOORE R

IPC: G05D3/12 ,  H01J37/304 ,  H01L21/027 ,  G01N23/00

Abstract: 1508903 Wave energy position finding INTERNATIONAL BUSINESS MACHINES CORP 23 May 1975 [27 June 1974] 22919/75 Heading G1A [Also in Division H4] The position of a registration mark on a target (e.g. a semi-conductor wafer) is detected by irradiating the mark with a beam of charged particles. The present invention is stated to be an improvement over the system described in Specification 1480562. As described, each mark 42, Fig. 17, consists of vertical and horizontal bars 44, 43 (raised portions or depressions), the position of the mark being determined from 20 horizontal (X) scans followed by 20 vertical (Y) scans, successive scans being in opposite directions. Peak signals corresponding to the edges of a bar are detected and applied to threshold circuitry which is updated during each scan. Diodes 45, 46 and 45', 46' detect radiation during X, Y scans respectively, the arrangement including extra diodes 47 and an extra lead going to a respective preamplifier 48-66 for noise suppression. X-scanning: The outputs 70, 71 from diodes 45, 46 contain peaks 72 &c. corresponding to the edges of a bar 44. These signals pass to a differential amplifier 69 via balancers 58, 60 which compensate for the fact that the mark being scanned will be nearer one diode than the other. The output 85, Fig. 13, from amplifier 69 contains positive and negative peaks 86, 87 corresponding to the edges of a bar. The signals are shown without any ramp component. Such component is removed in filter 89 to leave the peak signals plus a substantially constant residual baseline voltage, Figs. 14 and 15 (not shown). The output from filter 89 is fed via an AGC circuit 90 to positive and negative peak detectors 99, 100 and an averaging circuit 122. During the first scan, outputs 103, 104 from detectors 99, 100 are used to set the gain levels in AGC 90 for subsequent scans so as to compensate for the surface conditions on the wafer in the region of the mark being scanned. At the end of the first scan the contents of 99, 100, 122 are passed to stores 143, 128, 136 the outputs of which are combined by means of resistors 144, 140, 137 to produce positive and negative threshold signals 134 and 141 which are correlated with the residual baseline voltage. These signals pass via differential amplifiers 135, 142 to act as threshold levels for voltage comparators 118, 119 receiving signals from AGC 90 via a switch 116 (blocked during the first scan). During the second scan, fresh data is fed to detectors 99 &c. and stores 143 &c. and switch 116 is enabled to pass the output of AGC 90 to the comparators, outputs of which are however not used until the third scan. During the third and subsequent scans, comparators 118, 119 produce signals whenever the signals from AGC 90 cross the levels set during the preceding scan by amplifiers 135, 142. The ORed outputs from 118, 119 enable a gate 151, so that clockpulses 153 pass to a feedback channel 152 and a computer 19 which uses the detected-edge signals, averaged over the last 18 scans, to determine the location of mark 42. Since successive scans occur in opposite directions, stores 143, 136 incorporate means for reversing the sign of their outputs, so that detectors 99, 100 continue to detect the same edge of a bar 44 during successive scans. The Y-scan is then performed in the same way. The various blocks of Fig. 2 are described in detail with reference to Figs. 3-9 (not shown).

公开(公告)号：CA935887A

公开(公告)日：1973-10-23

申请号：CA100051

申请日：1970-12-08

Applicant: IBM

Inventor： MOORE R ,  DAVIDSON E

IPC: G11C11/41 ,  G11C11/39 ,  H01L27/07 ,  H03K3/35

Abstract: This application discloses a storage cell which employs a single gated multi-emitter semiconductor device that exhibits a negative resistance operating characteristic. The semiconductor device is biased to have two stable operating states on this negative resistance characteristic and is addressed by a word line connected to one of its emitters and a bit line connected to the other of its emitters. A parasitic transistor is formed by the two emitters and the gating layer of the semiconductor device. By application of half-select pulses to the word and bit lines, the parasitic transistor is broken down to cause a temporary current flow in the gating region of the semiconductor device. While this current flows in the gating region, the operating characteristic of the semiconductor device is changed so that there is only one stable operating state for the semiconductor device. The operation of the semiconductor device therefore shifts to this single operating state. When the temporary current flow ends the semiconductor device will be in a low voltage, high current stable state along the negative resistance characteristic irrespective of the operating state of the semiconductor device prior to the application of the half select pulses. When such a storage cell is manufactured in monolithic form, very high cell densities and extremely high operating speeds are obtainable.