公开(公告)号：JPH08328827A

公开(公告)日：1996-12-13

申请号：JP13499796

申请日：1996-05-29

Applicant: IBM

Inventor： MAIKERU PATORITSUKU BIIKUSU ,  BAABARA AREIN CHIYATSUPERU ,  TERII AIBUAN CHIYATSUPERU ,  BURUUSU MAATEIN FUREISHIYAA ,  TAO GOKU GUUEN

IPC: G06F7/50 ,  G06F7/508 ,  H03K19/096

Abstract: PROBLEM TO BE SOLVED: To provide a self-resetting parallel binary adder which can perform addition and subtraction at high speeds while reducing the power consumption and generated di/dt noise. SOLUTION: An adder logical architecture is a carry lookahead for two-bit groups and requires a six-digit combinational logic circuit which calculates a carry from the most significant bit(MSB). The load to the critical path of an adder is reduced by shifting combinational circuits to rear lines as many as possible. The adder uses the logical architecture of a bubble pipeline circuit. For the adder, a bubble pipe segment is constituted of one row of self-resetting circuit blocks. By using the front-edge high-speed forward amplification of pulse input signals and quick self-resetting to the standby states of all succeeding nodes, high-speed cycle time and minimum delay are realized to each block.