公开(公告)号：JPH04229488A

公开(公告)日：1992-08-18

申请号：JP16940591

申请日：1991-06-14

Applicant: IBM

Inventor： BAABARA AREN CHIYATSUPERU ,  TERII AIBUAN CHIYATSUPERU ,  MAHAMUTO KEMARU EBUSHIOGURU ,  SUTANREI EBUERETSUTO SHIYUSUTA

IPC: G06F12/08 ,  G06F12/00 ,  G06F12/04 ,  G06F12/0855 ,  G11C8/12 ,  G11C8/16 ,  G11C11/41

Abstract: PURPOSE: To provide a multiport RAM structure combining speed, density and multi-port function which can not be balanced with both a conventional multiport RAM and a the multidata copy in a conventional single port RAM. CONSTITUTION: The virtual multiport RAM structure 10 executed as a pipelined semiconductor memory chip has multiaddresses respectively multiplexed in address busses and data busses, a single port RAM array being on the chip given by a data input port and an internal timing device on the chip controlling the timing of the single port array and also cycling the multiinput ports in order to perform the multiport RAM function.

公开(公告)号：JPH08328827A

公开(公告)日：1996-12-13

申请号：JP13499796

申请日：1996-05-29

Applicant: IBM

Inventor： MAIKERU PATORITSUKU BIIKUSU ,  BAABARA AREIN CHIYATSUPERU ,  TERII AIBUAN CHIYATSUPERU ,  BURUUSU MAATEIN FUREISHIYAA ,  TAO GOKU GUUEN

IPC: G06F7/50 ,  G06F7/508 ,  H03K19/096

Abstract: PROBLEM TO BE SOLVED: To provide a self-resetting parallel binary adder which can perform addition and subtraction at high speeds while reducing the power consumption and generated di/dt noise. SOLUTION: An adder logical architecture is a carry lookahead for two-bit groups and requires a six-digit combinational logic circuit which calculates a carry from the most significant bit(MSB). The load to the critical path of an adder is reduced by shifting combinational circuits to rear lines as many as possible. The adder uses the logical architecture of a bubble pipeline circuit. For the adder, a bubble pipe segment is constituted of one row of self-resetting circuit blocks. By using the front-edge high-speed forward amplification of pulse input signals and quick self-resetting to the standby states of all succeeding nodes, high-speed cycle time and minimum delay are realized to each block.

公开(公告)号：JPH08123661A

公开(公告)日：1996-05-17

申请号：JP22873795

申请日：1995-09-06

Applicant: IBM

Inventor： BAABARA ARAN CHIYATSUPERU ,  TERII AIBUAN CHIYATSUPERU ,  BURUUSU MAATEIN FUREISHIYAA ,  SUTANREI EBUARETSUTO SHIYUUSUT

IPC: G06F7/04 ,  G06F7/02

Abstract: PROBLEM TO BE SOLVED: To provide a comparator circuit which can operate with reliability with the small number of stages. SOLUTION: The high-speed comparator circuit is provided with plural first switches XOR operating in parallel. First and second data words are inputted to the first switches. When the data words are matched, a first logic state output is given. When they are not matched, a second logic state output is given. The plural second switches receive the logic state outputs and give combined outputs showing that the whole words are matched or they are not matched to first switches 82 and 84. The third switches are connected to first and second branch nodes 44 and 46, generate a first voltage difference between the first and second branch nodes when the whole words are matched, and generate a second voltage difference when they are not matched. A sense amplifier amplifies the voltage difference which becomes large in accordance with imbalance generated in the conduction of the two branch nodes.