公开(公告)号：DE69021092T2

公开(公告)日：1996-02-29

申请号：DE69021092

申请日：1990-01-11

Applicant: IBM

Inventor： BAILEY ROGER NED ,  MANSFIELD ROBERT LOCKWOOD ,  SPENCER ALEXANDER KOOS

IPC: G06F13/36 ,  G06F13/28

公开(公告)号：DE69021092D1

公开(公告)日：1995-08-31

申请号：DE69021092

申请日：1990-01-11

Applicant: IBM

Inventor： BAILEY ROGER NED ,  MANSFIELD ROBERT LOCKWOOD ,  SPENCER ALEXANDER KOOS

IPC: G06F13/36 ,  G06F13/28

公开(公告)号：DE68925466T2

公开(公告)日：1996-08-14

申请号：DE68925466

申请日：1989-10-31

Applicant: IBM

Inventor： BAILEY ROGER NED ,  MANSFIELD ROBERT LOCKWOOD ,  SPENCER ALEXANDER KOOS

IPC: G06F11/30 ,  G04G15/00 ,  G06F1/14 ,  G06F11/00

Abstract: A timer circuit includes a counter circuit that continuously provides an output of an iteratively increasing sequence of bits. The timer includes a timeout data circuit that forms a timeout data word from a specified time period and a first counter circuit output. A register is provided that stores the timeout data word at an address formed from a second counter circuit output. A comparison circuit is provided that compares each counter output with a timeout data word at the address formed from that counter output and provides a timeout signal when they are equal. This timer includes a constantly incrementing counter to address a register that includes a multiple of timeout condition specifications, and as a determination of when the timeout conditions stored in the register occur.

公开(公告)号：DE68925466D1

公开(公告)日：1996-02-29

申请号：DE68925466

申请日：1989-10-31

Applicant: IBM

Inventor： BAILEY ROGER NED ,  MANSFIELD ROBERT LOCKWOOD ,  SPENCER ALEXANDER KOOS

IPC: G06F11/30 ,  G04G15/00 ,  G06F1/14 ,  G06F11/00

Abstract: A timer circuit includes a counter circuit that continuously provides an output of an iteratively increasing sequence of bits. The timer includes a timeout data circuit that forms a timeout data word from a specified time period and a first counter circuit output. A register is provided that stores the timeout data word at an address formed from a second counter circuit output. A comparison circuit is provided that compares each counter output with a timeout data word at the address formed from that counter output and provides a timeout signal when they are equal. This timer includes a constantly incrementing counter to address a register that includes a multiple of timeout condition specifications, and as a determination of when the timeout conditions stored in the register occur.