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    1.
    发明专利
    未知

    公开(公告)号：DE68925466T2

    公开(公告)日：1996-08-14

    申请号：DE68925466

    申请日：1989-10-31

    Applicant: IBM

    Inventor： BAILEY ROGER NED ,  MANSFIELD ROBERT LOCKWOOD ,  SPENCER ALEXANDER KOOS

    IPC: G06F11/30 ,  G04G15/00 ,  G06F1/14 ,  G06F11/00

    Abstract: A timer circuit includes a counter circuit that continuously provides an output of an iteratively increasing sequence of bits. The timer includes a timeout data circuit that forms a timeout data word from a specified time period and a first counter circuit output. A register is provided that stores the timeout data word at an address formed from a second counter circuit output. A comparison circuit is provided that compares each counter output with a timeout data word at the address formed from that counter output and provides a timeout signal when they are equal. This timer includes a constantly incrementing counter to address a register that includes a multiple of timeout condition specifications, and as a determination of when the timeout conditions stored in the register occur.

    2.
    发明专利
    未知

    公开(公告)号：DE68925466D1

    公开(公告)日：1996-02-29

    申请号：DE68925466

    申请日：1989-10-31

    Applicant: IBM

    Inventor： BAILEY ROGER NED ,  MANSFIELD ROBERT LOCKWOOD ,  SPENCER ALEXANDER KOOS

    IPC: G06F11/30 ,  G04G15/00 ,  G06F1/14 ,  G06F11/00

    Abstract: A timer circuit includes a counter circuit that continuously provides an output of an iteratively increasing sequence of bits. The timer includes a timeout data circuit that forms a timeout data word from a specified time period and a first counter circuit output. A register is provided that stores the timeout data word at an address formed from a second counter circuit output. A comparison circuit is provided that compares each counter output with a timeout data word at the address formed from that counter output and provides a timeout signal when they are equal. This timer includes a constantly incrementing counter to address a register that includes a multiple of timeout condition specifications, and as a determination of when the timeout conditions stored in the register occur.

    9.
    发明专利
    未知

    公开(公告)号：DE3889136T2

    公开(公告)日：1994-11-17

    申请号：DE3889136

    申请日：1988-01-26

    Applicant: IBM

    Inventor： GUPTA SATISH ,  LUMELSKY LEON ,  MANSFIELD ROBERT LOCKWOOD ,  ROMERO HECTOR GERARDO ,  SEGRE MARC ,  SPENCER ALEXANDER KOOS ,  ST CLAIR JOE CHRISTOPHER ,  WAGONER JAMES DONALD

    IPC: G06F3/153 ,  G06T11/20 ,  G09G5/393 ,  G09G1/16

    Abstract: As the speed and capacity of graphics workstations and personal computers including graphics adapters increases, a display adapter which can be used either in such a high capacity stand alone graphics workstation or in conjunction with a large main frame host computer includes a first processor for managing adapter resources and controlling coordinate transformations; a system storage for storing instructions and data representing information to be displayed; a first-in, first-out input buffer for allowing asynchronous and overlapped communication between the graphics system and a host computer;a second processor for drawing vectors and manipulating areas to be displayed on the monitor;a frame buffer connected to the second processor for storing a bit map of data to be displayed; a colour palette connected to outputs of the frame buffer for providing appropriate colour signals to the monitor; and a hardware cursor circuit for controlling display of a cursor on the monitor.

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