公开(公告)号：IT1148833B

公开(公告)日：1986-12-03

申请号：IT2242680

申请日：1980-05-30

Applicant: IBM

Inventor： BAKER CURETON DAVID ,  BANTZ DAVID FREDERICK ,  EVANGELISTI CARLO JOHN

IPC: G06F12/02 ,  G06F12/06 ,  G06F13/14 ,  G06F13/16 ,  G06F13/36 ,  G06F15/16 ,  G06F15/173 ,  G06F

Abstract: The technique for transmitting address information between a processor and a plurality of memory subsystems in a common bus communication system. The width of the address field is greater than the number of lines on the bus. For example, addresses are three bytes wide, and the bus is one byte wide, thereby reducing the number of pins required on the processor and the subsystems. For communication between the processor and a given memory subsystem, only those bytes of a selected address which differ from the corresponding bytes of a previous address are transmitted sequentially for accessing a selected memory location.