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    2.
    发明专利
    未知

    公开(公告)号：DE3685065D1

    公开(公告)日：1992-06-04

    申请号：DE3685065

    申请日：1986-07-18

    Applicant: IBM

    Inventor： BANTZ DAVID FREDERICK ,  EVANGELISTI CARLO JOHN

    IPC: G06F3/153 ,  G06F3/048 ,  G06F3/14 ,  G06F17/50 ,  G06T1/00 ,  G06T11/00 ,  G06T15/06 ,  G06T15/40 ,  G09G5/14 ,  G09G1/00 ,  G06F15/72

    Abstract: In a method for rapid windowing of display information in a computer system image data is maintained in a hierarchical data tree structure. The complete image field (1), within which the image is defined, is divided into cells (7). The window is defined within this field and a field of possible interest (5) is defined around the window. Then, for each node in the tree, summary node data is computed which identifies those cells within the field of possible interest which are at least partially occupied by the part of the image defined at that node. By traversing the tree it is then possible to identify rapidly the image data to be windowed.

    3.
    发明专利
    未知

    公开(公告)号：IT1149865B

    公开(公告)日：1986-12-10

    申请号：IT2639680

    申请日：1980-12-03

    Applicant: IBM

    Inventor： BANTZ DAVID FREDERICK ,  EVANGELISTI CARLO JOHN ,  NELSON ROBERT ARTHUR

    IPC: G06F11/22 ,  G01R31/317 ,  G01R31/3185 ,  G06F11/267 ,  G06F11/36 ,  G06G

    Abstract: An arrangement is described comprising a diagnostic computer (11) connected to a host computer (12) for the purpose of troubleshooting the host computer's hardware and software. The arrangement includes an interface unit (13) comprising specific controls (31, 33, 35) with transfer and mask registers between the diagnostic computer and the host, and control units (22, 23) in the diagnostic computer, to perform functions required by the user of the system. The arrangement is specifically designed for use with a host computer comprising a level-sensitive scan (LSSD) register.

    4.
    发明专利
    未知

    公开(公告)号：DE2652869A1

    公开(公告)日：1977-06-16

    申请号：DE2652869

    申请日：1976-11-20

    Applicant: IBM

    Inventor： BELADY LASZLO ANTAL ,  EVANGELISTI CARLO JOHN

    IPC: G06F12/14 ,  G06F11/30 ,  G06F11/34 ,  G06F12/00 ,  G06F21/00 ,  G07C1/00 ,  G06F11/10

    Abstract: 1534189 Monitoring storage accesses INTERNATIONAL BUSINESS MACHINES CORP 16 Nov 1976 [4 Dec 1975] 47656/76 Heading G4A A memory 12 or 32 is divided into envelopes 12a-12f or 34 each of which has an associated storage element 18 or 30 in which a time stamp from a clock 20 is recorded each time that envelope is accessed. Time stamp recording is automatic so that by reading the time stamps for particular memory elements a user can determine if any unauthorized access has been made since the last authorized access. Memory 12 may be a random access memory of which time stamp registers 18 form a part. Memory 32 may be a magnetic disc unit having two envelopes 34 and associated time stamp words 30 per track. The arrangement is described in detail in the context of a virtual memory system in which the time stamp registers 18 form an associative memory which is searched by block registers and stores time stamps together with indications as to whether the relevant accesses were for read or write. Any time stamp register 18 can be read by a special instruction FSM which loads the contents of the required register 18 into a specified register in the CPU 10. Each data channel 38 has a corresponding time stamp register 36 which is loaded with a time stamp word 30 whenever a disc envelope is moved via the channel to a memory 12 envelope (the appropriate register 18 and word 30 also time stamped from clock 20). The register 36 contents can be loaded into a specified CPU register by a special instruction FSC. Data envelope transfer between disc 32 and memory 12 takes place serially by word via a shift register buffer.

    5.
    发明专利
    未知

    公开(公告)号：IT8026396D0

    公开(公告)日：1980-12-03

    申请号：IT2639680

    申请日：1980-12-03

    Applicant: IBM

    Inventor： BANTZ DAVID FREDERICK ,  EVANGELISTI CARLO JOHN ,  NELSON ROBERT ARTHUR

    IPC: G06F11/22 ,  G01R31/317 ,  G01R31/3185 ,  G06F11/267 ,  G06F11/36 ,  G06G

    Abstract: An arrangement is described comprising a diagnostic computer (11) connected to a host computer (12) for the purpose of troubleshooting the host computer's hardware and software. The arrangement includes an interface unit (13) comprising specific controls (31, 33, 35) with transfer and mask registers between the diagnostic computer and the host, and control units (22, 23) in the diagnostic computer, to perform functions required by the user of the system. The arrangement is specifically designed for use with a host computer comprising a level-sensitive scan (LSSD) register.

    DATA PROCESSING SYSTEM
    6.
    发明专利
    DATA PROCESSING SYSTEM 未知

    公开(公告)号：GB1292568A

    公开(公告)日：1972-10-11

    申请号：GB1362371

    申请日：1971-05-07

    Applicant: IBM

    Inventor： EVANGELISTI CARLO JOHN ,  RITTENHOUSE LARRY EDWARD

    IPC: G06F17/30 ,  G11B20/12 ,  G11B27/10 ,  G11B27/11 ,  G11B27/32

    Abstract: 1292568 Storage addressing system INTERNATIONAL BUSINESS MACHINES CORP 7 May 1971 [12 June 1970] 13623/71 Heading G4C A storage file, e.g. disc, drum, tape, delay line, is divided into blocks, each of which contains a plurality of data files and a directory containing the names of the data files in the block and their intra-block addresses, the data file names are used for pointing to the block in which the files are contained, a pointed-to block is accessed first at its directory to obtain the intra-block address of a desired data file by comparison of file names, and then at the remainder of the block to obtain the desired file by comparison of intra-block addresses. In the described embodiment, the file names are processed by a hashcoding algorithm to obtain the block pointers and while a disc transducing head is being moved to access the block containing the desired file, the file name is entered in a register 12. When the appropriate block is being accessed, its directory is searched in real time by reading the directory serially by bit into a shift register 10 and comparing the contents of one section of the register 10 with those of register 12 in a comparator 22. On detecting a match, the intra-block start address of the desired file and of the following file (or the file end address if the desired file is the last in the block) are transferred to registers 14, 16 for subsequent comparison with an incremented intra-block address register 18 which is started when the end of the directory is reached. The begin and stop read signals from comparators 28, 32 are used to transfer the desired file from shift register 10 to an output device. By adding duplicate circuits, more than one file may be accessed from a block in a single seek and read operation, and the files may be of variable length.

    7.
    发明专利
    未知

    公开(公告)号：DE3855377D1

    公开(公告)日：1996-07-25

    申请号：DE3855377

    申请日：1988-11-24

    Applicant: IBM

    Inventor： EVANGELISTI CARLO JOHN ,  LUMELSKY LEON ,  PAVICIC MARK JOSEPH

    IPC: G06T15/50 ,  G06T15/40

    Abstract: The present invention comprises a method for utilizing an socalled SIMD computer architecture in conjunction with a host processor and coordinate processor to render quality, three-dimensional, anti-aliased shaded color images into the frame buffer of a video display system. The method includes a parallel algorithm for rendering an important graphic primitive for accomplishing the production of a smoothly shaded color three-dimensional triangle with anti-aliased edges. By taking advantage of the SIMD architecture and said parallel algorithm, the very time consuming pixel by pixel computations are broken down for parallel execution. A single coordinate processor computes and transmits an overall triangle record which is essentially the same for all blocks of pixels within a given bounding box which box in turn surrounds each triangle. The individual pixel data is produced by a group of M x N pixel processors and stored in the frame buffer in a series of repetitive steps wherein each step corresponds to the processing of an M x N block of pixels within the bounding box of the triangle. Thus, each pixel processor performs the same operation, modifying its computations in accordance with triangle data received from the coordinate processor and positional data unique to its own sequential connectivity to the frame buffer, thus allowing parallel access to the frame buffer.

    8.
    发明专利
    未知

    公开(公告)号：IT1148833B

    公开(公告)日：1986-12-03

    申请号：IT2242680

    申请日：1980-05-30

    Applicant: IBM

    Inventor： BAKER CURETON DAVID ,  BANTZ DAVID FREDERICK ,  EVANGELISTI CARLO JOHN

    IPC: G06F12/02 ,  G06F12/06 ,  G06F13/14 ,  G06F13/16 ,  G06F13/36 ,  G06F15/16 ,  G06F15/173 ,  G06F

    Abstract: The technique for transmitting address information between a processor and a plurality of memory subsystems in a common bus communication system. The width of the address field is greater than the number of lines on the bus. For example, addresses are three bytes wide, and the bus is one byte wide, thereby reducing the number of pins required on the processor and the subsystems. For communication between the processor and a given memory subsystem, only those bytes of a selected address which differ from the corresponding bytes of a previous address are transmitted sequentially for accessing a selected memory location.

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