公开(公告)号：DE3580511D1

公开(公告)日：1990-12-20

申请号：DE3580511

申请日：1985-04-17

Applicant: IBM

Inventor： BARRY ROBERT LLOYD

IPC: H03K19/013 ,  G11C7/10 ,  H03K17/60 ,  H03K17/62 ,  H03K19/086 ,  H03K19/094 ,  H03K19/0952 ,  G11C7/00

Abstract: A dual mode logic circuit for selectively coupling first and second inputs to first and second outputs. The circuit comprises first gating means for coupling said first input to both said first and second outputs and second gating means for coupling said first input to said first output and for coupling said second input to said second output. The circuit is controlled by means for selectively activating said first or said second gating means.

公开(公告)号：DE3586840T2

公开(公告)日：1993-06-09

申请号：DE3586840

申请日：1985-09-17

Applicant: IBM

Inventor： ANDERSEN JOHN EDWARD ,  BARRY ROBERT LLOYD ,  CHRISTIE KENNETH HOWARD ,  SHEA DENNIS JOHN

IPC: G06F12/08 ,  G06F17/30 ,  G06F15/40 ,  G11C15/04

Abstract: The memory system includes a plurality of reconfigurable subarrays of memory cells (SUBO...SUB3) and having the capability of simultaneously performing write/compare, read/compare, compare/bypass, write/bypass, or write/compare/bypass operations. The present system may be fabricated on a single integrated circuit chip and includes circuitry for selectively writing data into the subarrays (12, WD10...WD18, BD0...BD3, WS0...WS3). Output data from the subarrays (SUB0...SUB3) is connected to compare data logic (CL10...CL13, CL20...CL23) for comparing the subarray data to one or more bytes of compare input data, and to bit select logic (BS0...BS3) for selectively placing the subarray data onto an output bus. Bypass select logic (24) causes either the subarray data or one byte of compare data to be output from the memory system data output port. In one embodiment, two bytes of compare input data can be simultaneously compared with a selected data byte from each of the subarrays (SUB0...SUB3), and one byte of compare input data can be bypassed to the data output port during the compare operation. Additionally, data may be written into the subarrays (SUBO...SUB3) while simultaneously performing the compare or the compare/bypass operations.

公开(公告)号：DE69007496D1

公开(公告)日：1994-04-21

申请号：DE69007496

申请日：1990-10-05

Applicant: IBM

Inventor： ANDERSEN JOHN EDWARD ,  BARRY ROBERT LLOYD ,  BISNETT JAMES ,  FUNG ERIC

IPC: G11C11/411 ,  G11C11/416

Abstract: A memory cell responsive to a write enable signal for storing write signals present on a pair of write bit lines and responsive to a read enable signal for presenting stored data on a pair of read sense lines further includes a timed, active write load. The memory cell includes first and second NPN bipolar transistors having commonly connected emitters, and cross-coupled bases and collectors; and first and second PNP bipolar transistors configured as loads for the pair of NPN bipolar transistors. Write transistors are provided responsive to the write enable signal for draining current from a selected one of the first or second nodes. Transistors connected as diodes between the PNP bases and each of the cross-coupled NPN nodes are responsive to the current draining effected by the write transistors for biasing both of the first and second PNP transistors into an active mode of operation.

公开(公告)号：SG128429A1

公开(公告)日：2007-01-30

申请号：SG200202675

申请日：2002-05-06

Applicant: IBM

Inventor： EUSTIS STEVEN MICHAEL ,  BARRY ROBERT LLOYD ,  CROCE PETER FRANCIS

IPC: G06F12/00 ,  G06F13/00 ,  G11C7/00 ,  G11C8/00

Abstract: A memory circuit design efficiently obtains predictable array output when an invalid address is requested. The memory circuit component (200) comprises an invalid word line path (212), in addition to a standard valid word line path (207). To provide correct output, a dummy word line output (208) of a first decode logic (205) is delayed (209A), and the delayed dummy word line output (210) is ANDed (213) with a word line output (207) to update the data out latch (217). Further, the invalid word line output (212) of a second decode logic (211) is also delayed (209B), and the delayed invalid word line output (214) is ORed (215) with the delayed dummy word line output (210) to reset the control logic (219). ORing (215) the delayed signals allows the predictable output to be provided at a common clock time, irrespective of whether a valid address or an invalid address is decoded.

公开(公告)号：DE69007496T2

公开(公告)日：1994-09-29

申请号：DE69007496

申请日：1990-10-05

Applicant: IBM

Inventor： ANDERSEN JOHN EDWARD ,  BARRY ROBERT LLOYD ,  BISNETT JAMES ,  FUNG ERIC

IPC: G11C11/411 ,  G11C11/416

Abstract: A memory cell responsive to a write enable signal for storing write signals present on a pair of write bit lines and responsive to a read enable signal for presenting stored data on a pair of read sense lines further includes a timed, active write load. The memory cell includes first and second NPN bipolar transistors having commonly connected emitters, and cross-coupled bases and collectors; and first and second PNP bipolar transistors configured as loads for the pair of NPN bipolar transistors. Write transistors are provided responsive to the write enable signal for draining current from a selected one of the first or second nodes. Transistors connected as diodes between the PNP bases and each of the cross-coupled NPN nodes are responsive to the current draining effected by the write transistors for biasing both of the first and second PNP transistors into an active mode of operation.

公开(公告)号：DE3586840D1

公开(公告)日：1992-12-24

申请号：DE3586840

申请日：1985-09-17

Applicant: IBM

Inventor： ANDERSEN JOHN EDWARD ,  BARRY ROBERT LLOYD ,  CHRISTIE KENNETH HOWARD ,  SHEA DENNIS JOHN

IPC: G06F12/08 ,  G06F17/30 ,  G06F15/40 ,  G11C15/04

Abstract: The memory system includes a plurality of reconfigurable subarrays of memory cells (SUBO...SUB3) and having the capability of simultaneously performing write/compare, read/compare, compare/bypass, write/bypass, or write/compare/bypass operations. The present system may be fabricated on a single integrated circuit chip and includes circuitry for selectively writing data into the subarrays (12, WD10...WD18, BD0...BD3, WS0...WS3). Output data from the subarrays (SUB0...SUB3) is connected to compare data logic (CL10...CL13, CL20...CL23) for comparing the subarray data to one or more bytes of compare input data, and to bit select logic (BS0...BS3) for selectively placing the subarray data onto an output bus. Bypass select logic (24) causes either the subarray data or one byte of compare data to be output from the memory system data output port. In one embodiment, two bytes of compare input data can be simultaneously compared with a selected data byte from each of the subarrays (SUB0...SUB3), and one byte of compare input data can be bypassed to the data output port during the compare operation. Additionally, data may be written into the subarrays (SUBO...SUB3) while simultaneously performing the compare or the compare/bypass operations.