公开(公告)号：DE3586840T2

公开(公告)日：1993-06-09

申请号：DE3586840

申请日：1985-09-17

Applicant: IBM

Inventor： ANDERSEN JOHN EDWARD ,  BARRY ROBERT LLOYD ,  CHRISTIE KENNETH HOWARD ,  SHEA DENNIS JOHN

IPC: G06F12/08 ,  G06F17/30 ,  G06F15/40 ,  G11C15/04

Abstract: The memory system includes a plurality of reconfigurable subarrays of memory cells (SUBO...SUB3) and having the capability of simultaneously performing write/compare, read/compare, compare/bypass, write/bypass, or write/compare/bypass operations. The present system may be fabricated on a single integrated circuit chip and includes circuitry for selectively writing data into the subarrays (12, WD10...WD18, BD0...BD3, WS0...WS3). Output data from the subarrays (SUB0...SUB3) is connected to compare data logic (CL10...CL13, CL20...CL23) for comparing the subarray data to one or more bytes of compare input data, and to bit select logic (BS0...BS3) for selectively placing the subarray data onto an output bus. Bypass select logic (24) causes either the subarray data or one byte of compare data to be output from the memory system data output port. In one embodiment, two bytes of compare input data can be simultaneously compared with a selected data byte from each of the subarrays (SUB0...SUB3), and one byte of compare input data can be bypassed to the data output port during the compare operation. Additionally, data may be written into the subarrays (SUBO...SUB3) while simultaneously performing the compare or the compare/bypass operations.

公开(公告)号：DE3586840D1

公开(公告)日：1992-12-24

申请号：DE3586840

申请日：1985-09-17

Applicant: IBM

Inventor： ANDERSEN JOHN EDWARD ,  BARRY ROBERT LLOYD ,  CHRISTIE KENNETH HOWARD ,  SHEA DENNIS JOHN

IPC: G06F12/08 ,  G06F17/30 ,  G06F15/40 ,  G11C15/04

Abstract: The memory system includes a plurality of reconfigurable subarrays of memory cells (SUBO...SUB3) and having the capability of simultaneously performing write/compare, read/compare, compare/bypass, write/bypass, or write/compare/bypass operations. The present system may be fabricated on a single integrated circuit chip and includes circuitry for selectively writing data into the subarrays (12, WD10...WD18, BD0...BD3, WS0...WS3). Output data from the subarrays (SUB0...SUB3) is connected to compare data logic (CL10...CL13, CL20...CL23) for comparing the subarray data to one or more bytes of compare input data, and to bit select logic (BS0...BS3) for selectively placing the subarray data onto an output bus. Bypass select logic (24) causes either the subarray data or one byte of compare data to be output from the memory system data output port. In one embodiment, two bytes of compare input data can be simultaneously compared with a selected data byte from each of the subarrays (SUB0...SUB3), and one byte of compare input data can be bypassed to the data output port during the compare operation. Additionally, data may be written into the subarrays (SUBO...SUB3) while simultaneously performing the compare or the compare/bypass operations.