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公开(公告)号:AU1672500A
公开(公告)日:2000-07-03
申请号:AU1672500
申请日:1999-12-10
Inventor: BAUMGARTNER YOANNA , DEAN MARK EDWARD , ELMAN ANNA
Abstract: A non-uniform memory access (NUMA) computer system includes at least a local processing node and a remote processing node that are each coupled to a node interconnect. The local processing node includes a local interconnect, a processor and a system memory coupled to the local interconnect, and a node controller interposed between the local interconnect and the node interconnect. In response to receipt of a read request from the local interconnect, the node controller speculatively transmits the read request to the remote processing node via the node interconnect. Thereafter, in response to receipt of a response to the read request from the remote processing node, the node controller handles the response in accordance with a resolution of the read request at the local processing node. For example, in one processing scenario, data contained in the response received from the remote processing node is discarded by the node controller if the read request received a Modified Intervention coherency response at the local processing node.
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公开(公告)号:PL348859A1
公开(公告)日:2002-06-17
申请号:PL34885999
申请日:1999-12-10
Inventor: BAUMGARTNER YOANNA , DEAN MARK EDWARD , ELMAN ANNA
Abstract: A non-uniform memory access (NUMA) computer system includes at least a local processing node and a remote processing node that are each coupled to a node interconnect. The local processing node includes a local interconnect, a processor and a system memory coupled to the local interconnect, and a node controller interposed between the local interconnect and the node interconnect. In response to receipt of a read request from the local interconnect, the node controller speculatively transmits the read request to the remote processing node via the node interconnect. Thereafter, in response to receipt of a response to the read request from the remote processing node, the node controller handles the response in accordance with a resolution of the read request at the local processing node. For example, in one processing scenario, data contained in the response received from the remote processing node is discarded by the node controller if the read request received a Modified Intervention coherency response at the local processing node.
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公开(公告)号:HU0104577A2
公开(公告)日:2002-03-28
申请号:HU0104577
申请日:1999-12-10
Inventor: BAUMGARTNER YOANNA , DEAN MARK EDWARD , ELMAN ANNA
Abstract: A non-uniform memory access (NUMA) computer system includes at least a local processing node and a remote processing node that are each coupled to a node interconnect. The local processing node includes a local interconnect, a processor and a system memory coupled to the local interconnect, and a node controller interposed between the local interconnect and the node interconnect. In response to receipt of a read request from the local interconnect, the node controller speculatively transmits the read request to the remote processing node via the node interconnect. Thereafter, in response to receipt of a response to the read request from the remote processing node, the node controller handles the response in accordance with a resolution of the read request at the local processing node. For example, in one processing scenario, data contained in the response received from the remote processing node is discarded by the node controller if the read request received a Modified Intervention coherency response at the local processing node.
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公开(公告)号:CA2280172C
公开(公告)日:2006-04-18
申请号:CA2280172
申请日:1999-08-12
Applicant: IBM
Inventor: ELMAN ANNAN , BAUMGARTNER YOANNA , HARRIS GLEN DOUGLAS
IPC: G06F15/173 , G06F15/17
Abstract: A non-uniform memory access (NUMA) computer system includes at least a local processing node and a remote processing node that are each coupled to a node interconnect. The local processing node includes at least a processor and a local system memory, and the remote processing node includes at least a processor having an associated cache memory, a loca l system memory, and a node controller that are each coupled to a local interconnect. In response to receipt by the node controller of a request transaction transmitted from the local processing no de via the node interconnect, the node controller at the remote processing node issues the request transaction on the local interconnect. If the request transaction receives a retry response at the remote processing node, the node controller does not immediately return the retry response to the local processing node. Instead, the node controller reissues the request transaction on the local interconnect at least once, thus giving the request transaction another opportunity to complete successfully. In one embodiment, the request transaction is reissued on the local interconnect of the remote processing node until a response other than retry is received or until a retry limit is reached.
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公开(公告)号:ES2196893T3
公开(公告)日:2003-12-16
申请号:ES99959592
申请日:1999-12-10
Applicant: IBM
Inventor: BAUMGARTNER YOANNA , DEAN MARK EDWARD , ELMAN ANNA
Abstract: A non-uniform memory access (NUMA) computer system includes at least a local processing node and a remote processing node that are each coupled to a node interconnect. The local processing node includes a local interconnect, a processor and a system memory coupled to the local interconnect, and a node controller interposed between the local interconnect and the node interconnect. In response to receipt of a read request from the local interconnect, the node controller speculatively transmits the read request to the remote processing node via the node interconnect. Thereafter, in response to receipt of a response to the read request from the remote processing node, the node controller handles the response in accordance with a resolution of the read request at the local processing node. For example, in one processing scenario, data contained in the response received from the remote processing node is discarded by the node controller if the read request received a Modified Intervention coherency response at the local processing node.
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公开(公告)号:AT236431T
公开(公告)日:2003-04-15
申请号:AT99959592
申请日:1999-12-10
Applicant: IBM
Inventor: BAUMGARTNER YOANNA , DEAN MARK EDWARD , ELMAN ANNA
Abstract: A non-uniform memory access (NUMA) computer system includes at least a local processing node and a remote processing node that are each coupled to a node interconnect. The local processing node includes a local interconnect, a processor and a system memory coupled to the local interconnect, and a node controller interposed between the local interconnect and the node interconnect. In response to receipt of a read request from the local interconnect, the node controller speculatively transmits the read request to the remote processing node via the node interconnect. Thereafter, in response to receipt of a response to the read request from the remote processing node, the node controller handles the response in accordance with a resolution of the read request at the local processing node. For example, in one processing scenario, data contained in the response received from the remote processing node is discarded by the node controller if the read request received a Modified Intervention coherency response at the local processing node.
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7.
公开(公告)号:CA2291401C
公开(公告)日:2005-04-26
申请号:CA2291401
申请日:1999-12-02
Applicant: IBM
Inventor: BAUMGARTNER YOANNA , ELMAN ANNA
Abstract: A non-uniform memory access (NUMA) computer system includes first and seco nd processing nodes that are coupled together. The first processing node includ es a system memory and first and second processors that each have a respective associated cache hierarchy. The second processing node includes at least a third processor and a system memory. If the cache hierarchy of the first processor holds an unmodified copy of a cache line and receives a request for the cache line from the third processor, the cache hierarchy of the first processor sources the requested cache line to the third processor and retains a copy of the cache line in a Recent coherency state from which the cache hierarchy of the first processor can source the cache line in response to subsequent requests.
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公开(公告)号:CA2280172A1
公开(公告)日:2000-03-21
申请号:CA2280172
申请日:1999-08-12
Applicant: IBM
Inventor: BAUMGARTNER YOANNA , ELMAN ANNAN , HARRIS GLEN DOUGLAS
IPC: G06F15/17 , G06F15/173
Abstract: A non-uniform memory access (NUMA) computer system includes at least a local processing node and a remote processing node that are each coupled to a node interconnect. The local processing node includes at least a processor and a local system memory, and the remote processing node includes at least a processor having an associated cache memory, a local system memory, and a node controller that are each coupled to a local interconnect. In response to receipt by the node controller of a request transaction transmitted from the local processing node via the node interconnect, the node controller at the remote processing node issues the request transaction on the local interconnect. If the request transaction receives a retry response at the remote processing node, the node controller does not immediately return the retry response to the local processing node. Instead, the node controller reissues the request transaction on the local interconnect at least once, thus giving the request transaction another opportunity to complete successfully. In one embodiment, the request transaction is reissued on the local interconnect of the remote processing node until a response other than retry is received or until a retry limit is reached.
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公开(公告)号:DE69906585T2
公开(公告)日:2004-02-12
申请号:DE69906585
申请日:1999-12-10
Applicant: IBM
Inventor: BAUMGARTNER YOANNA , DEAN EDWARD , ELMAN ANNA
Abstract: A non-uniform memory access (NUMA) computer system includes at least a local processing node and a remote processing node that are each coupled to a node interconnect. The local processing node includes a local interconnect, a processor and a system memory coupled to the local interconnect, and a node controller interposed between the local interconnect and the node interconnect. In response to receipt of a read request from the local interconnect, the node controller speculatively transmits the read request to the remote processing node via the node interconnect. Thereafter, in response to receipt of a response to the read request from the remote processing node, the node controller handles the response in accordance with a resolution of the read request at the local processing node. For example, in one processing scenario, data contained in the response received from the remote processing node is discarded by the node controller if the read request received a Modified Intervention coherency response at the local processing node.
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公开(公告)号:CZ20012153A3
公开(公告)日:2001-09-12
申请号:CZ20012153
申请日:1999-12-10
Applicant: IBM
Inventor: BAUMGARTNER YOANNA , DEAN MARK EDWARD , ELMAN ANNA
Abstract: A non-uniform memory access (NUMA) computer system includes at least a local processing node and a remote processing node that are each coupled to a node interconnect. The local processing node includes a local interconnect, a processor and a system memory coupled to the local interconnect, and a node controller interposed between the local interconnect and the node interconnect. In response to receipt of a read request from the local interconnect, the node controller speculatively transmits the read request to the remote processing node via the node interconnect. Thereafter, in response to receipt of a response to the read request from the remote processing node, the node controller handles the response in accordance with a resolution of the read request at the local processing node. For example, in one processing scenario, data contained in the response received from the remote processing node is discarded by the node controller if the read request received a Modified Intervention coherency response at the local processing node.
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