NONSYNCHRONOUS CHANNEL/DASD COMMUNICATION SYSTEM

    公开(公告)号:CA2046720A1

    公开(公告)日:1992-03-01

    申请号:CA2046720

    申请日:1991-07-10

    Applicant: IBM

    Abstract: A control unit (12) for DASD operation to transfer data between the device (13) and a buffer (16) and between a channel (11) and a buffer (16). In that manner the channel and device are enabled to transfer data independently of each other. Mechanisms are provided for communication between the channel interface process in the control unit and the device interface process in the control unit. Some of these mechanisms are stored with the record in the buffer and others are stored in control storage. Principle communicating mechanisms include a device record pointer, a channel record pointer, a next operation field, a device state indicator, record control flags, and two buffer pointers.

    ERROR CONTROL IN A HIERARCHICAL SYSTEM

    公开(公告)号:CA1168365A

    公开(公告)日:1984-05-29

    申请号:CA397742

    申请日:1982-03-05

    Applicant: IBM

    Abstract: A hierarchical communication system has multipaths for different levels of the hierarchy, each set of paths is assigned a criticalness to the successful operation of the system. Error races for all of the paths are monitored. A threshold for defining an unusable data path is based upon the criticalness of the path to successful operation. That is, the more critical the path, the higher the error rate that will be sustained. A specific embodiment employs shift-registers for indicating the error rate of the last predetermined number of usages of the given paths. A mass storage system employing the error-rate system is described. TU981008

    MANAGING HIGH SPEED SLOW ACCESS CHANNEL TO SLOW SPEED CYCLIC SYSTEM DATA TRANSFERS

    公开(公告)号:CA2046709A1

    公开(公告)日:1992-03-01

    申请号:CA2046709

    申请日:1991-07-10

    Applicant: IBM

    Abstract: A cached DASD controller is illustrated which is attached to a high speed serial channel, such as an optical fiber channel. The data rate of the serial channel is much greater than the data rate of a DASD connected to the controller. The serial channel has a relatively long propagation time such that synchronous operations between the host processor 10 and the DASD cannot be efficiently performed. Operation of a data transfer, whether read or write between the host processor 10 and the DASD is monitored. Whenever a copy of the track contents is in cache and the DASD reaches either an index mark with or a break point from a roll mode operation or certain write operations occur resulting in predetermined data being stored in cache, then a GOCACHE flag is set in a control portion of the controller. The device operations are then momentarily idled while cache to host processor operations are enabled.

    DEVICE INITIATED PARTIAL SYSTEM QUIESCING

    公开(公告)号:CA1299757C

    公开(公告)日:1992-04-28

    申请号:CA570926

    申请日:1988-06-30

    Applicant: IBM

    Abstract: A data processing system includes a plurality of host systems and peripheral subsystems, particularly data storage subsystems. Each of the data storage subsystems includes a plurality of control units attaching a plurality of data storage devices such as direct access storage devices (DASD) for storing data on behalf of the various host systems. Each of the control units have a separate storage path for accessing the peripheral data storage devices using dynamic pathing. The storage paths can be clustered into power clusters. Maintenance personnel acting through maintenance panels on either the control units or the peripheral data storage devices activate the subsystem to request reconfiguration of the subsystem from all of the host systems connected to the subsystem. The host systems can honor the request or reject it based upon diverse criteria. Upon each of the host systems approving the reconfiguration, the subsystem is reconfigured for maintenance purposes. Upon completion of the maintenance procedures, a second reconfiguration request is sent to the host systems for causing quiesce devices to resume normal operations. TU986011

    NONSYNCHRONOUS DASD CONTROL
    10.
    发明专利

    公开(公告)号:CA2046708A1

    公开(公告)日:1992-03-01

    申请号:CA2046708

    申请日:1991-07-10

    Applicant: IBM

    Abstract: Apparatus is disclosed for controlling a disk drive or DASD in a manner that is not synchronous with channel operation, that is, transfer of commands and data are not limited to inter-record gaps periods. A device interface processor controls which recording track is accessed by the DASD with data being transferred to and from a buffer. A device track indicator designates which recording tracks the device will move to in sequence. A channel interface processor controls the movement of data from and to the buffer and channel. A channel track indicator designates the recording track sequence in which the channel interface processor will access the data to be transferred. A method of operation is also disclosed for utilizing the two indicators to enable the device and channel processors to communicate with each other in case the device reads incorrect records in a multi-track read operation.

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