公开(公告)号：CA2046709A1

公开(公告)日：1992-03-01

申请号：CA2046709

申请日：1991-07-10

Applicant: IBM

Inventor： BEARDSLEY BRENT C ,  BENHASE MICHAEL T ,  CANDELARIA SUSAN K

IPC: G06F3/06 ,  G06F12/08

Abstract: A cached DASD controller is illustrated which is attached to a high speed serial channel, such as an optical fiber channel. The data rate of the serial channel is much greater than the data rate of a DASD connected to the controller. The serial channel has a relatively long propagation time such that synchronous operations between the host processor 10 and the DASD cannot be efficiently performed. Operation of a data transfer, whether read or write between the host processor 10 and the DASD is monitored. Whenever a copy of the track contents is in cache and the DASD reaches either an index mark with or a break point from a roll mode operation or certain write operations occur resulting in predetermined data being stored in cache, then a GOCACHE flag is set in a control portion of the controller. The device operations are then momentarily idled while cache to host processor operations are enabled.