公开(公告)号：JPH08115204A

公开(公告)日：1996-05-07

申请号：JP25150395

申请日：1995-09-28

Applicant: IBM

Inventor： BECHADE ROLAND ALBERT

IPC: G06F7/00 ,  G06F7/74

Abstract: PROBLEM TO BE SOLVED: To discriminate the total number of pieces of preceding '0' or '1' in a binary data field, especially, in a fixed-size field. SOLUTION: A device for discriminating the number of preceding binary data bits incorporates a plurality of detector circuits which input the different sections of a binary data field. During the course of preceding '0' detecting operations, each detector circuit discriminates the bit position containing the highest-order '1' of the binary data field and outputs a binary number signal indicating the number of '0' preceding the highest-order '1'. The detector circuit also discriminates whether or not each bit position in the section which is inputted by the circuit itself contains '0', and outputs a zero detecting signal indicating the state. The binary number signal and zero detecting signal respectively generate a binary number signal indicating the number of preceding '0' in a complete binary field and a zero detecting signal indicating whether or not all bit positions in the complete binary field contain '0'.

公开(公告)号：BR8706010A

公开(公告)日：1988-07-19

申请号：BR8706010

申请日：1987-11-09

Applicant: IBM

Inventor： BECHADE ROLAND ALBERT ,  KINGHOFFMANN WILLIAM ,  OGILVIE CLARENCE ROSSER

IPC: G06F7/53 ,  G06F7/508 ,  G06F7/52

公开(公告)号：DE68918810T2

公开(公告)日：1995-04-27

申请号：DE68918810

申请日：1989-11-16

Applicant: IBM

Inventor： BECHADE ROLAND ALBERT ,  OGILVIE CLARENCE ROSSER

IPC: H03K17/00 ,  H03K17/693 ,  H03K17/62

Abstract: A circuit is provided, of the multiplexer type, which includes pass gates having first and second P-channel field effect transistors (P1, P2) and first and second N-channel field effect transistors (N1, N2), a first data signal (D1) is applied to first current-carrying electrodes of the first P-channel and first N-channel transistors with a second data signal (D2) applied to first current-carrying electrodes of the second P-channel and second N-channel transistors, second current-carrying electrodes of the first and second P-channel transistors being connected together and second current-carrying electrodes of the first and second N-channel transistors being connected together and coupled to the second current-carrying electrodes of the first and second P-channel transistors. A true control pulse (A) is applied to control electrodes of the first N-channel transistor and of the second P-channel transistor and a complemented control pulse is applied to control electrodes of the first P-channel transistors and of the second N-channel transistor. An output of the circuit is coupled to the second current-carrying electrodes of the transistors to selectively receive the first and second data signals. Further embodiments of the circuit provide for an extended number of data signal inputs.

公开(公告)号：DE68918810D1

公开(公告)日：1994-11-17

申请号：DE68918810

申请日：1989-11-16

Applicant: IBM

Inventor： BECHADE ROLAND ALBERT ,  OGILVIE CLARENCE ROSSER

IPC: H03K17/00 ,  H03K17/693 ,  H03K17/62

Abstract: A circuit is provided, of the multiplexer type, which includes pass gates having first and second P-channel field effect transistors (P1, P2) and first and second N-channel field effect transistors (N1, N2), a first data signal (D1) is applied to first current-carrying electrodes of the first P-channel and first N-channel transistors with a second data signal (D2) applied to first current-carrying electrodes of the second P-channel and second N-channel transistors, second current-carrying electrodes of the first and second P-channel transistors being connected together and second current-carrying electrodes of the first and second N-channel transistors being connected together and coupled to the second current-carrying electrodes of the first and second P-channel transistors. A true control pulse (A) is applied to control electrodes of the first N-channel transistor and of the second P-channel transistor and a complemented control pulse is applied to control electrodes of the first P-channel transistors and of the second N-channel transistor. An output of the circuit is coupled to the second current-carrying electrodes of the transistors to selectively receive the first and second data signals. Further embodiments of the circuit provide for an extended number of data signal inputs.