公开(公告)号：BR8706010A

公开(公告)日：1988-07-19

申请号：BR8706010

申请日：1987-11-09

Applicant: IBM

Inventor： BECHADE ROLAND ALBERT ,  KINGHOFFMANN WILLIAM ,  OGILVIE CLARENCE ROSSER

IPC: G06F7/53 ,  G06F7/508 ,  G06F7/52

公开(公告)号：GB2523870A

公开(公告)日：2015-09-09

申请号：GB201419302

申请日：2014-10-30

Applicant: IBM

Inventor： VENTRONE SEBASTIAN THEODORE ,  GOODNOW KENNETH JOSEPH ,  OGILVIE CLARENCE ROSSER ,  WOODRUFF CHARLES ,  GRAF RICHARD STEPHEN

IPC: H01L25/065 ,  H01L21/768 ,  H01L23/48

Abstract: A heat conductive layer 308 is deposited on a first surface of a wafer of semiconductor chips 332. An insulating layer 312 is then deposited on top of the heat conducting layer. The heat conductive layer is etched to form vias that expose through-electrodes 305 on the first surface of each semiconductor chip. Conductive pads 316 are deposited on the through-electrodes on a second surface of each semiconductor chip. The semiconductor chips are stacked, wherein the conductive bumps of a second one of the semiconductor chips electrically contact the through-electrodes of a first one of the semiconductor chips through the vias of the first semiconductor chip and the conductive bumps of a third one of the semiconductor chips electrically contact the through-electrodes of the second semiconductor chip through the vias of the second semiconductor chip. The holes in the thermally conductive layer and the insulating layer may be formed by etching. The through electrodes may be copper pillars and an underfill may be applied between the bottom semiconductor chip and a substrate.

公开(公告)号：DE68918810T2

公开(公告)日：1995-04-27

申请号：DE68918810

申请日：1989-11-16

Applicant: IBM

Inventor： BECHADE ROLAND ALBERT ,  OGILVIE CLARENCE ROSSER

IPC: H03K17/00 ,  H03K17/693 ,  H03K17/62

Abstract: A circuit is provided, of the multiplexer type, which includes pass gates having first and second P-channel field effect transistors (P1, P2) and first and second N-channel field effect transistors (N1, N2), a first data signal (D1) is applied to first current-carrying electrodes of the first P-channel and first N-channel transistors with a second data signal (D2) applied to first current-carrying electrodes of the second P-channel and second N-channel transistors, second current-carrying electrodes of the first and second P-channel transistors being connected together and second current-carrying electrodes of the first and second N-channel transistors being connected together and coupled to the second current-carrying electrodes of the first and second P-channel transistors. A true control pulse (A) is applied to control electrodes of the first N-channel transistor and of the second P-channel transistor and a complemented control pulse is applied to control electrodes of the first P-channel transistors and of the second N-channel transistor. An output of the circuit is coupled to the second current-carrying electrodes of the transistors to selectively receive the first and second data signals. Further embodiments of the circuit provide for an extended number of data signal inputs.

公开(公告)号：DE68918810D1

公开(公告)日：1994-11-17

申请号：DE68918810

申请日：1989-11-16

Applicant: IBM

Inventor： BECHADE ROLAND ALBERT ,  OGILVIE CLARENCE ROSSER

IPC: H03K17/00 ,  H03K17/693 ,  H03K17/62

Abstract: A circuit is provided, of the multiplexer type, which includes pass gates having first and second P-channel field effect transistors (P1, P2) and first and second N-channel field effect transistors (N1, N2), a first data signal (D1) is applied to first current-carrying electrodes of the first P-channel and first N-channel transistors with a second data signal (D2) applied to first current-carrying electrodes of the second P-channel and second N-channel transistors, second current-carrying electrodes of the first and second P-channel transistors being connected together and second current-carrying electrodes of the first and second N-channel transistors being connected together and coupled to the second current-carrying electrodes of the first and second P-channel transistors. A true control pulse (A) is applied to control electrodes of the first N-channel transistor and of the second P-channel transistor and a complemented control pulse is applied to control electrodes of the first P-channel transistors and of the second N-channel transistor. An output of the circuit is coupled to the second current-carrying electrodes of the transistors to selectively receive the first and second data signals. Further embodiments of the circuit provide for an extended number of data signal inputs.