公开(公告)号：DE2962989D1

公开(公告)日：1982-07-22

申请号：DE2962989

申请日：1979-06-01

Applicant: IBM

Inventor： BEILSTEIN JR KENNETH E ,  KOTECHA HARISH N

IPC: G11C17/00 ,  G11C11/34 ,  G11C11/56 ,  G11C16/04 ,  G11C17/12 ,  H03K19/094 ,  G11C11/40

Abstract: A quaternary FET read only memory is disclosed wherein each FET storage element in the array has its threshold adjusted by ion-implantation to one of four values. Each FET element in the array has its drain connected to a drain potential VDD. A binary input signal from a conventional binary, true/complement generator will then enable the gate of a selected FET storage cell and the output potential at the source of that selected storage cell will be VDD minus the customized threshold voltage of that storage cell, which is output at an output node. The signal on the output node is a quaternary signal which may be amplified by a quaternary sense amplifier circuit and then converted from quaternary to binary signal by means of a converter. The quaternary read only memory is capable of storing twice as much information per unit area as is a conventional FET binary read only memory. The concept may be expanded to N levels of information storage, using FET array devices with N different threshold voltages.