公开(公告)号：DE3071925D1

公开(公告)日：1987-04-16

申请号：DE3071925

申请日：1980-11-10

Applicant: IBM

Inventor： KOTECHA HARISH N ,  DE LA MONEDA FRANCISCO H

IPC: H01L29/78 ,  H01L21/033 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L21/00

Abstract: A DMOS field effect transistor device and fabrication process is disclosed whereby a precisely defined channel length is generated between a source region (44a) and a drain region (46a) of a second conductivity type within a substrate of a first conductivity type. … A first ion-implanted region (68) in said channel region is connected to said source region (44a), said first ion-implanted region being of said first conductivity type and forming an enhancement mode region of a predetermined threshold voltage. … A second ion-implanted region (86) in said channel region is connected to said drain region (46a), said second ion-implanted region being of said second conductivity type and forming a depletion mode drain extension. … The ends of the implanted regions defining the channel length are determined by a lateral etching technique by means of which the implantation mask is generated.

公开(公告)号：FR2384389A1

公开(公告)日：1978-10-13

申请号：FR7804183

申请日：1978-02-08

Applicant: IBM

Inventor： BEILSTEIN KENNETH E JR ,  KOTECHA HARISH N

IPC: H01L21/822 ,  H01L21/761 ,  H01L21/8236 ,  H01L27/04 ,  H01L27/088 ,  H03K17/687 ,  H03K19/094 ,  H03K19/0944 ,  H03K19/40 ,  H03K19/08

公开(公告)号：DE3473531D1

公开(公告)日：1988-09-22

申请号：DE3473531

申请日：1984-12-11

Applicant: IBM

Inventor： FREDERICKS EDWARD CARMINE ,  KOTECHA HARISH N

IPC: H01L21/306 ,  H01L21/027 ,  H01L21/265 ,  H01L21/266 ,  H01L21/312 ,  H01L21/316 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/00

公开(公告)号：DE2963294D1

公开(公告)日：1982-08-26

申请号：DE2963294

申请日：1979-08-07

Applicant: IBM

Inventor： HELLER LAWRENCE GRIFFITH ,  JONES HARRY JORDAN ,  KOTECHA HARISH N ,  SODERMAN DONALD ARVID

IPC: H01L21/339 ,  H01L21/265 ,  H01L21/8234 ,  H01L27/07 ,  H01L27/105 ,  H01L29/762 ,  H01L27/10 ,  H01L21/82 ,  H01L27/06

公开(公告)号：DE2739586A1

公开(公告)日：1978-03-23

申请号：DE2739586

申请日：1977-09-02

Applicant: IBM

Inventor： DE LA MONEDA FRANCISCO H ,  KOTECHA HARISH N

IPC: H01L21/822 ,  H01L21/82 ,  H01L21/8238 ,  H01L27/04 ,  H01L27/088 ,  H01L27/092 ,  H01L29/78 ,  H03K17/687 ,  H03K19/094 ,  H03K19/0944 ,  H03K19/0948 ,  H03K19/08 ,  H03K17/04 ,  H01L27/08

Abstract: An insulated Gate Field Effect Transistor (IGFET) static inverter having an improved load line characteristic is disclosed. The inverter comprises an enhancement mode IGFET active device in a first portion of a semiconductor substrate, having its drain connected to an output node, its source connected to a source potential and its gate connected to an input signal source. The first portion of the substrate is connected to a first substrate potential. A depletion mode IGFET load device is located in a second portion of the semiconductor substrate which is electrically isolated from the first portion. The depletion mode load device has its drain connected to a drain potential and its source, gate and the second portion of the semiconductor substrate all connected to the output node. In this manner, the rise in the source-to-substrate voltage bias during the turn-off transition is eliminated in the depletion mode load device, providing an improved load current characteristic for the inverter. Alternate embodiments are disclosed directed to an all N-channel inverter, an all P-channel inverter, and a complementary inverter consisting of a P-channel load device and an N-channel active device.

公开(公告)号：DE3372045D1

公开(公告)日：1987-07-16

申请号：DE3372045

申请日：1983-10-05

Applicant: IBM

Inventor： BRACCO AL M ,  EDENFELD ARTHUR R ,  KOTECHA HARISH N

IPC: H01L29/78 ,  H01L21/8246 ,  H01L27/112 ,  H01L27/10 ,  H01L21/82

Abstract: A polycrystalline silicon gate (6) is manufactured on a substrate (2), then a chemical vapor deposition (CVD) oxide (14, 18) applied, covering the sidewalls (10, 12) of each of the gates (6),. An ion implantation step is then carried out to implant source and drain regions (22, 24) whose proximate edges (26, 30) are not aligned with the edges of the gate (6), due to the masking effect of the sidewall portion of the CVD oxide. Thereafter, the CVD oxide is selectively removed for those FET device locations (A) where an active FET device is desired to be formed, i.e. the ROM/PLA is personalized. Those locations are then ion implanted for source and drain extensions (34, 38) which are aligned with the edges of the gate (6). The process enables a significantly reduced turnaround time for personalizing ROMs or PLAs which contain FET memory devices. The FETs have a shorter channel length, higher breakdown voltage characteristic, an almost zero channel hot electron effect, and a lower gate-to-source/drain diffusion overlap capacitance than most other FET read only memory devices.

公开(公告)号：CA1149064A

公开(公告)日：1983-06-28

申请号：CA372695

申请日：1981-03-10

Applicant: IBM

Inventor： KOTECHA HARISH N

IPC: H01L27/112 ,  G11C16/04 ,  G11C17/00 ,  H01L21/8246 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40

Abstract: LOW VOLTAGE ELECTRICALLY ERASABLE PROGRAMMABLE READ ONLY MEMORY An improved memory system is provided for charging and discharging a conductive plate such as a floating gate of a field effect transistor with a charge injector controlled by a low single polarity voltage pulse. In the system of the invention, the conductive plate may be a floating gate of a field effect transistor which also includes first and second or dual control gates. A single or double graded band gap layer, such as a silicon rich layer of silicon dioxide is disposed only between the floating gate and the first control gate forming a capacitor having a given capacitance with a larger capacitor disposed between the second control gate and the floating gate. These cells or transistors may be used in an array for storing for long periods of time, on the order of 10 years or more, binary digits of information representing a 0 or a 1 depending upon whether a charge is stored on the floating ate. When using these cells in a memory array, information may be written into or erased from each of the cells individually or a blanket erase may be employed for the entire or a selected section of the array. To write and to erase a cell, a low single polarity voltage is employed. Several embodiments of the invention are disclosed including one embodiment wherein the dual gates are located on one side of the floating gate, a second embodiment which uses a diffusion in a semiconductor substrate as one of the control gates and a third embodiment wherein one of the control gates is disposed on one side of, or above, the floating gate and the other control gate is disposed on the other side of, or below, the floating gate near the surface of the channel region of the transistor. BU9-80-010

公开(公告)号：FR2389233A1

公开(公告)日：1978-11-24

申请号：FR7809185

申请日：1978-03-23

Applicant: IBM

Inventor： MONEDA FRANCISCO H DE LA ,  KOTECHA HARISH N

IPC: H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/74 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/417 ,  H01L29/45 ,  H01L29/78 ,  H01L21/82

公开(公告)号：DE3381333D1

公开(公告)日：1990-04-19

申请号：DE3381333

申请日：1983-06-16

Applicant: IBM

Inventor： KOTECHA HARISH N

IPC: G11C17/00 ,  G11C11/00 ,  G11C11/401 ,  G11C14/00 ,  G11C17/12 ,  G11C29/00 ,  G11C29/04 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L27/112 ,  G11C11/24

Abstract: A combined read-only storage (ROS) and read/write random access memory (RAM) integrated circuit memory cell is disclosed. In a first cell embodiment, a ROS FET device (ROS,) and a RAM FET device (RAM 1 ) are connected in common to a bit sensing line (BL2) connected to a sense amplifier which senses if the ROS FET device has discharged the bit sensing line (BL2) indicating that a gate is present on the ROS FET device. A write driver circuit (32) is also connected to the bit sensing line (BL2), for providing current through the RAM FET device to the charge storage element for writing a one or a zero therein. In a second cell embodiment, a combined two-bit read-only storage and one-bit read/write random access memory integrated circuit cell is disclosed. The bit sensing line is shared by two ROS FET devices and one RAM FET device. In a third cell embodiment of the invention, a single binary bit is stored for read-only storage and a single binary bit is stored for read/write random access memory storage. The charge storage element shares a common node with the ROS FET device and the RAM FET device and the sense amplifier is connected to the opposite side of the RAM FET device.

公开(公告)号：DE2962989D1

公开(公告)日：1982-07-22

申请号：DE2962989

申请日：1979-06-01

Applicant: IBM

Inventor： BEILSTEIN JR KENNETH E ,  KOTECHA HARISH N

IPC: G11C17/00 ,  G11C11/34 ,  G11C11/56 ,  G11C16/04 ,  G11C17/12 ,  H03K19/094 ,  G11C11/40

Abstract: A quaternary FET read only memory is disclosed wherein each FET storage element in the array has its threshold adjusted by ion-implantation to one of four values. Each FET element in the array has its drain connected to a drain potential VDD. A binary input signal from a conventional binary, true/complement generator will then enable the gate of a selected FET storage cell and the output potential at the source of that selected storage cell will be VDD minus the customized threshold voltage of that storage cell, which is output at an output node. The signal on the output node is a quaternary signal which may be amplified by a quaternary sense amplifier circuit and then converted from quaternary to binary signal by means of a converter. The quaternary read only memory is capable of storing twice as much information per unit area as is a conventional FET binary read only memory. The concept may be expanded to N levels of information storage, using FET array devices with N different threshold voltages.