公开(公告)号：AU4192478A

公开(公告)日：1979-06-14

申请号：AU4192478

申请日：1978-11-24

Applicant: IBM

Inventor： BEISMANN WALTER F ,  LAMPE HANS H ,  POHLE WERNER H

IPC: G06F9/48 ,  G06F9/18

Abstract: In a microprogram controlled processor a master mask signal, generated selectively under microprogram control, synchronizes the handling of asynchronously generated interruption requests to desired sequence stages in the interpretation of program instructions. A programmed interrupt request (PIRR) associated with the interruption priority level of the program currently in control of the processor is maintained effective for a limited period of time after the associated program assumes control. This period is determined by the presence of a PIRR (-bit) which is interruptable by any higher priority level interrupt request. If a PIRR bit representing an interrupted program is still on when servicing of a higher priority level interrupt request is concluding control is returned to the interrupted program. In order to avoid possibly locking out programs which are not associated with asynchronously generated interrupt requests-e.g., supervisor programs-a pre-settable interval timer is provided for operating after a predetermined time interval to force the setting of a PIRR bit and thereby force control to be transferred eventually to such programs.

公开(公告)号：FR2411442A1

公开(公告)日：1979-07-06

申请号：FR7830983

申请日：1978-10-24

Applicant: IBM

Inventor： BEISMANN WALTER F ,  LAMPE HANS H ,  POHLE WERNER H

IPC: G06F9/48 ,  G06F9/18

Abstract: In a microprogram controlled processor a master mask signal, generated selectively under microprogram control, synchronizes the handling of asynchronously generated interruption requests to desired sequence stages in the interpretation of program instructions. A programmed interrupt request (PIRR) associated with the interruption priority level of the program currently in control of the processor is maintained effective for a limited period of time after the associated program assumes control. This period is determined by the presence of a PIRR (-bit) which is interruptable by any higher priority level interrupt request. If a PIRR bit representing an interrupted program is still on when servicing of a higher priority level interrupt request is concluding control is returned to the interrupted program. In order to avoid possibly locking out programs which are not associated with asynchronously generated interrupt requests-e.g., supervisor programs-a pre-settable interval timer is provided for operating after a predetermined time interval to force the setting of a PIRR bit and thereby force control to be transferred eventually to such programs.

公开(公告)号：FR2373100A1

公开(公告)日：1978-06-30

申请号：FR7731536

申请日：1977-10-07

Applicant: IBM

Inventor： BEISMANN WALTER F ,  LAMPE HANS H ,  POHLE WERNER H

IPC: G01R31/3183 ,  G06F11/22 ,  G06F11/04

Abstract: A method for error analysis and diagnosis uses error images stored in the system from which significant error information is extracted by analyzing the error bytes of the error image. The error information is combined, via tables, with error information extracted from other error bytes and a reference code is generated by the combination by means of which a predetermined error file is addressed, which contains information on the kind of error, its location and information on the remedying of the error.

公开(公告)号：CH637230A5

公开(公告)日：1983-07-15

申请号：CH1117378

申请日：1978-10-30

Applicant: IBM

Inventor： BEISMANN WALTER F ,  LAMPE HANS H ,  POHLE WERNER H

IPC: G06F9/48 ,  G06F9/46

公开(公告)号：CA1115851A

公开(公告)日：1982-01-05

申请号：CA317422

申请日：1978-12-05

Applicant: IBM

Inventor： BEISMANN WALTER F ,  LAMPE HANS H ,  POHLE WERNER H

IPC: G06F9/48 ,  G06F9/00

Abstract: ARRANGEMENT FOR PROGRAM INTERRUPTION In a microprogram controlled processor a master mask signal, generated selectively under microprogram control, synchronizes the handling of asynchronously generated interruption requests to desired sequence stages in the interpretation of program instructions. A programmed interrupt request (PIRR) associated with the interruption priority level of the program currently in control of the processor is maintained effective for a limited period of time after the associated program assumes control. This period is determined by the presence of a PIRR (-bit) which is interruptable by any higher priority level interrupt request. If a PIRR bit representing an interrupted program is still on when servicing of a higher priority level interrupt request is concluding control is returned to the interrupted program. In order to avoid possibly locking out programs which are not associated with asynchronously generated interrupt requests -- e.g., supervisor programs -- a pre-settable interval timer is provided for operating after a predetermined time interval to force the setting of a PIRR bit and thereby force control to be transferred eventually to such programs. GE9-76-023

公开(公告)号：FR2411442B1

公开(公告)日：1986-01-31

申请号：FR7830983

申请日：1978-10-24

Applicant: IBM

Inventor： BEISMANN WALTER F ,  LAMPE HANS H ,  POHLE WERNER H

IPC: G06F9/48 ,  G06F9/18

Abstract: In a microprogram controlled processor a master mask signal, generated selectively under microprogram control, synchronizes the handling of asynchronously generated interruption requests to desired sequence stages in the interpretation of program instructions. A programmed interrupt request (PIRR) associated with the interruption priority level of the program currently in control of the processor is maintained effective for a limited period of time after the associated program assumes control. This period is determined by the presence of a PIRR (-bit) which is interruptable by any higher priority level interrupt request. If a PIRR bit representing an interrupted program is still on when servicing of a higher priority level interrupt request is concluding control is returned to the interrupted program. In order to avoid possibly locking out programs which are not associated with asynchronously generated interrupt requests-e.g., supervisor programs-a pre-settable interval timer is provided for operating after a predetermined time interval to force the setting of a PIRR bit and thereby force control to be transferred eventually to such programs.

公开(公告)号：DE2754890A1

公开(公告)日：1979-06-13

申请号：DE2754890

申请日：1977-12-09

Applicant: IBM DEUTSCHLAND

Inventor： BEISMANN WALTER F ,  LAMPE HANS HERMANN ,  POHLE WERNER HERBERT

IPC: G06F9/48 ,  G06F9/18

Abstract: In a microprogram controlled processor a master mask signal, generated selectively under microprogram control, synchronizes the handling of asynchronously generated interruption requests to desired sequence stages in the interpretation of program instructions. A programmed interrupt request (PIRR) associated with the interruption priority level of the program currently in control of the processor is maintained effective for a limited period of time after the associated program assumes control. This period is determined by the presence of a PIRR (-bit) which is interruptable by any higher priority level interrupt request. If a PIRR bit representing an interrupted program is still on when servicing of a higher priority level interrupt request is concluding control is returned to the interrupted program. In order to avoid possibly locking out programs which are not associated with asynchronously generated interrupt requests-e.g., supervisor programs-a pre-settable interval timer is provided for operating after a predetermined time interval to force the setting of a PIRR bit and thereby force control to be transferred eventually to such programs.